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8153f?avr?08/2013 features ? high-performance, low-power atmel? avr? xmega? 8/16-bit microcontroller ? nonvolatile program and data memories ? 8k ?32kbytes of in-system self-programmable flash ? 2k ? 4kbytes boot section ? 512bytes ? 1kbytes eeprom ? 1k ? 4kbytes internal sram ? peripheral features ? four-channel enhanced dma controller with 8/16-bit address match ? eight-channel event system ? asynchronous and synchronous signal routing ? quadrature encoder with rotary filter ? three 16-bit timer/counters ? one timer/counter with 4 output compare or input capture channels ? two timer/counter with 2 output compare or input capture channels ? high resolution extension enabling down to 4ns pwm resolution ? waveform extension for control of motor, led, lighting, h-bridge, high drives and more ? fault extension for safe and deterministic handling and/or shut-down of external driver ? crc-16 (crc-ccitt) and crc-32 (ieee 802.3) generator ? xmega custom logic (xcl) module with timer, counter and logic functions ? two 8-bit timer/counters with capture/compare and 16-bit cascade mode ? connected to one usart to support custom data frame length ? connected to i/o pins and event system to do programmable logic functions ? mux, and, nand, or, nor, xor, xnor, not, d-flip-flop, d latch, rs latch ? two usarts with full-duplex and single wire half-duplex configuration ? master spi mode ? support custom protocols with configurable data frame length up to 256-bit ? system wake-up from deep sleep modes when used with internal 8mhz oscillator ? one two-wire interface with dual address match (i 2 c and smbus compatible) ? bridge configuration for simultaneous master and slave operation ? up to 1mhz bus speed support ? one serial peripheral interface (spi) ? 16-bit real time counter with separate oscillator and digital correction ? one sixteen-channel, 12-bit, 300ksps analog to digital converter with: ? offset and gain correction ? averaging ? over-sampling and decimation ? one two-channel, 12-bit, 1msps digital to analog converter ? two analog comparators with window compare function and current sources ? external interrupts on all general purpose i/o pins ? programmable watchdog timer with separate on-chip ultra low power oscillator ? qtouch? library support ? capacitive touch buttons, sliders and wheels ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal and external clock options with pll ? programmable multilevel interrupt controller ? five sleep modes ? programming and debug interface ? pdi (program and debug interface) ? i/o and packages ? 26 programmable i/o pins ? 7x7mm 32-lead tqfp ? 5x5mm 32-lead vqfn ? 4x4mm 32-lead uqfn ? operating voltage ? 1.6 ? 3.6v ? operating frequency ? 0 ? 12mhz from 1.6v ? 0 ? 32mhz from 2.7v 8/16-bit atmel avr xmega microcontrollers atxmega32e5 / atxmega16e5 / atxmega8e5 preliminary
2 xmega e5 [datasheet] 8153f?avr?08/2013 1. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation. 2. pb-free packaging, complies to the european directive for restri ction of hazardous substances (rohs directive). also halide f ree and fully green. 3. for packaging information, see ?packaging information? on page 68 . 4. tape and reel 2. typical applications ordering code package (1)(2)(3) flash (bytes) eeprom (bytes) sram (bytes) speed (mhz) power supply temp. atxmega8e5-au 32a (7x7mm tqfp) 8k + 2k 512b 1k 32 1.6 ? 3.6v -40c ? 85c atxmega8e5-aur (4) atxmega8e5-mu 32z (5x5mm vqfn) atxmega8e5-mur (4) atxmega8e5-m4u 32ma (4x4mm uqfn) atxmega8e5-m4ur (4) atxmega16e5-au 32a (7x7mm tqfp) 16k + 4k 512b 2k 32 1.6 ? 3.6v -40c ? 85c atxmega16e5-aur (4) atxmega16e5-mu 32z (5x5mm vqfn) atxmega16e5-mur (4) atxmega16e5-m4u 32ma (4x4mm uqfn) atxmega16e5-m4ur (4) atxmega32e5-au 32a (7x7mm tqfp) 32k + 4k 1k 4k 32 1.6 ? 3.6v -40c ? 85c atxmega32e5aur (4) atxmega32e5-mu 32z (5x5mm vqfn) atxmega32e5-mur (4) atxmega32e5-m4u 32ma (4x4mm uqfn) atxmega32e5-m4ur (4) package type 32a 32-lead, 7x7mm body size, 1.0mm body thickness, 0.8mm l ead pitch, thin profile plastic quad flat package (tqfp) 32z 32-lead, 0.5mm pitch, 5x5mm very thin quad flat no lead package (vqfn) sawn 32ma 32-lead, 0.4mm pitch, 4x4x0.60mm ultr a thin quad no lead (uqfn) package board controller sensor control motor control user interface industrial control ballast control, inverters communication bridges battery charger utility metering appliances
3 xmega e5 [datasheet] 8153f?avr?08/2013 3. pinout and block diagram note: 1. for full details on pinout and alternate pin functions refer to ?pinout and pin functions? on page 57 . digital function analog function / oscillators programming, debug, test external clock / crystal pins general purpose i/o ground power pa4 pa3 pa2 pa1 pa0 2 3 4 5 6 gnd 1 avcc 32 31 pa6 pa5 pa7 30 29 28 27 26 25 pr1 pr0 20 19 vcc gnd 18 17 pdi 7 8 pd0 pd2 pd1 pd3 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 9 10 11 12 13 14 15 16 21 22 23 24 pd4 pd5 pd6 pd7 power supervision event routing network edma controller bus controller sram flash ocd prog/debug interface eeprom event system controller watchdog timer watchdog oscillator osc/clk control real time counter interrupt controller data bus data bus sleep controller reset controller tempref vref port r crc cpu port a adc ac0:1 aref port c tc4:5 usart 0 spi ircom port d tc5 usart0 twi adc dac xcl pdi / reset aref
4 xmega e5 [datasheet] 8153f?avr?08/2013 4. overview the atmel avr xmega is a family of low power, high perfo rmance, and peripheral rich 8/16-bit microcontrollers based on the avr enhanced risc architecture. by executing instructions in a single clock cycle, the avr xmega devices achieve cpu throughput approaching one million instructions per second (mips) per megahertz, allowing the system designer to optimize power consumption versus processing speed. the avr cpu combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumu lator or cisc based microcontrollers. the avr xmega e5 devices provide the following features : in-system programmable flash with read-while-write capabilities; internal eeprom and sram; four-channel e nhanced dma (edma) controller; eight-channel event system with asynchronous event support; programmable multilevel interrupt controller; 26 general purpose i/o lines; crc-16 (crc-ccitt) and crc-32 (ieee 802.3) generators; one xmega custom logic module with timer, counter and logic functions (xcl); 16-bit real-time counter (rtc) with digital correction; three flexible, 16-bit timer/counters with compare and pwm channels; two usarts; one two-wire serial interf ace (twi) allowing simultaneous master and slave; one serial peripheral interface (spi); one sixteen-channel, 12-bi t adc with programmable gain, offset and gain correction, averaging, over-sampling and decimation; one 2-channel 12-bi t dac; two analog comparators (acs) with window mode and current sources; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with pll and prescaler; and programmable brown-out detection. the program and debug interface (pdi), a fast, two-pi n interface for programming and debugging, is available. the avr xmega e5 devices have five software selectabl e power saving modes. the idle mode stops the cpu while allowing the sram, edma controller, event system, interrupt controller, and all peripherals to continue functioning. the power-down mode saves the sram and register contents, but stops the oscillators, disabling all other functions until the next twi, or pin-change interrupt, or reset. in power-save mo de, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. in standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. this allows very fast startup from the external crystal, combined with low power consumption. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. in each power save, standby or extended standby mode, the low power mode of the internal 8mhz oscillator allows very fast startup time combined with very low power consumption. to further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode and low power mode of the internal 8mhz oscillator can be enabled. atmel offers a free qtouch library for embedding capacitive touch buttons, sliders and wheels functionality into avr microcontrollers. the devices are manufactured using atme l high-density, nonvolatile memory technology. the program flash memory can be reprogrammed in-system through t he pdi. a boot loader running in the device can use any interface to download the application program to the flash memory. the boot loader software in the boot flash section can continue to run. by combining an 8/16-bit risc cpu with in-system, self-programmable flash, the avr xmega is a powerful microcontroller family that provides a highly flex ible and cost effective solution for many embedded applications. all atmel avr xmega devices are supported with a full suite of program and system development tools, including c compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
5 xmega e5 [datasheet] 8153f?avr?08/2013 5. resources a comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr . 5.1 recommended reading ? xmega? e manual ? xmega application notes this device data sheet only contains part specific informati on with a short description of each peripheral and module. the xmega e manual describes the modules and peripherals in depth. the xmega application notes contain example code and show applied use of the modules and peripherals. all documentations are available from www.atmel.com/avr . 6. capacitive touch sensing the atmel? qtouch? library provides a simple to use soluti on to realize touch sensitive interfaces on most atmel avr? microcontrollers. the patented charge-transfer signal acqui sition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppres sion? (aks?) technology for unambiguous detection of key events. the qtouch library includes support for the qtouch and qmatrix acquisition methods. touch sensing can be added to any application by linki ng the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch channels and sensors, and then calling the touch sensing api?s to retrieve the channel information and determine the touch sensor states. the atmel qtouch library is free and downloadable from the atmel website at the following location: http://www.atmel.com/tools/qtouchlibrary.aspx . for implementation details and other information, refer to the atmel qtouch library user guide - also available for download from the atmel website.
6 xmega e5 [datasheet] 8153f?avr?08/2013 7. cpu 7.1 features ? 8/16-bit, high-performance atmel avr risc cpu ? 142 instructions ? hardware multiplier ? 32x8-bit registers directly connected to the alu ? stack in ram ? stack pointer accessible in i/o memory space ? direct addressing of up to 16mb of program memory and 16mb of data memory ? true 16/24-bit access to 16/24-bit i/o registers ? efficient support for 8-, 16-, and 32-bit arithmetic ? configuration change protection of system-critical features 7.2 overview all avr xmega devices use the 8/16-bit avr cpu. the main function of the cpu is to execute the code and perform all calculations. the cpu is able to access memories, perform ca lculations, control peripherals, and execute the program in the flash memory. interrupt handling is described in a separate section, refer to ?interrupts and programmable multilevel interrupt controller? on page 27 . 7.3 architectural overview in order to maximize performance and parallelism, the avr cpu uses a harvard architecture with separate memories and buses for program and data. instructions in the program memo ry are executed with single-level pipelining. while one instruction is being executed, the next instruction is pre-fe tched from the program memory. this enables instructions to be executed on every clock cycle. for details of all avr instructions, refer to http://www.atmel.com/avr .
7 xmega e5 [datasheet] 8153f?avr?08/2013 figure 7-1. block diagram of the avr cpu architecture. the arithmetic logic unit (alu) supports arithmetic and l ogic operations between registers or between a constant and a register. single-register operations can also be executed in t he alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. the alu is directly connected to the fast-access register file. the 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmet ic logic unit (alu) operation between registers or between a register and an immediate. six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. the memory spaces are linear. the data memory space and the program memory space are two different memory spaces. the data memory space is divided into i/o registers, sram, and memory mapped eeprom. all i/o status and control registers reside in the lowest 4kb addresses of the data memory. this is referred to as the i/o memory space. the lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3f. the rest is the extended i/o memory space, ranging from 0x0040 to 0x0fff. i/o registers here must be accessed as data space locations using load (ld/lds/ldd) and store (st/sts/std) instructions. the sram holds data. code execution from sram is not s upported. it can easily be accessed through the five different addressing modes supported in the avr architecture. the first sram address is 0x2000. data addresses 0x1000 to 0x1fff are reserved for eeprom. the program memory is divided in two sections, the applic ation program section and the boot program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that is used for self- programming of the application flash memory must reside in t he boot program section. the application section contains an application table section with separate lock bits for write and read/write protection. the application table section can be used for save storing of nonvolatile data in the program memory.
8 xmega e5 [datasheet] 8153f?avr?08/2013 7.4 alu - arithmetic logic unit the arithmetic logic unit (alu) supports arithmetic and l ogic operations between registers or between a constant and a register. single-register operations can also be executed. the alu operates in direct connection with all 32 general purpose registers. in a single clock cycle, arithmetic oper ations between general purpose registers or between a register and an immediate are executed and the result is stored in the r egister file. after an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. alu operations are divided into three main categories ? ar ithmetic, logical, and bit functions. both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32- bit arithmetic. the hardware multiplier supports signed and unsigned multiplication and fractional format. 7.4.1 hardware multiplier the multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. the hardware multiplier supports different variations of signed and unsigned integer and fractional numbers: ? multiplication of unsigned integers ? multiplication of signed integers ? multiplication of a signed integer with an unsigned integer ? multiplication of unsigned fractional numbers ? multiplication of signed fractional numbers ? multiplication of a signed fractional number with an unsigned one a multiplication takes two cpu clock cycles. 7.5 program flow after reset, the cpu starts to execute instructions from t he lowest address in the flash program memory ?0.? the program counter (pc) addresses the next instruction to be fetched. program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. most avr instructions use a 16-bit word format, while a limited number use a 32-bit format. during interrupts and subroutine calls, the return address pc is stored on the stack. the stack is allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. after reset, the stack pointer (sp) points to the highest address in the internal sram. the sp is read/write accessible in the i/o memory space, enabling easy implementation of multiple stacks or stack areas. the data sram can easily be accessed through the five different addressing modes supported in the avr cpu. 7.6 status register the status register (sreg) contains information about the result of the most recently executed arithmetic or logic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specif ied in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when ente ring an interrupt routine nor restored when returning from an interrupt. this must be handled by software. the status register is accessible in the i/o memory space. 7.7 stack and stack pointer the stack is used for storing return addresses after interrupts and subroutine calls. it can also be used for storing temporary data. the stack pointer (sp) register always points to the top of the stack. it is implemented as two 8-bit registers that are accessible in the i/o memory space. data are pushed and popped from the stack using the push and pop instructions. the stack grows from a higher memory locati on to a lower memory location. this implies that pushing data onto the stack decreases the sp, and popping data off the stack increases the sp. the sp is automatically loaded
9 xmega e5 [datasheet] 8153f?avr?08/2013 after reset, and the initial value is the highest address of the internal sram. if the sp is changed, it must be set to point above address 0x2000, and it must be defined before any subr outine calls are executed or before interrupts are enabled. during interrupts or subroutine calls, the return address is automatically pushed on the stack. the return address can be two or three bytes, depending on program memory size of the device. for devices with 128kb or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. for devices with more than 128kb of program memory, the return address is three bytes, and hence the sp is decremented/incremented by three. the return address is popped off the stack when returning from interrupts using the reti instruction, and from subroutine calls using the ret instruction. the sp is decremented by one when data are pushed on the stack with the push instruction, and incremented by one when data is popped off the stack using the pop instruction. to prevent corruption when updating the stack pointer from software, a write to spl will automatically disable interrupts for up to four instructions or until the next i/o memory write. 7.8 register file the register file consists of 32 x 8-bit general purpose worki ng registers with single clock cycle access time. the register file supports the following input/output schemes: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input six of the 32 registers can be used as three 16-bit address r egister pointers for data space addressing, enabling efficient address calculations. one of these address pointers can also be used as an address pointer for lookup tables in flash program memory.
10 xmega e5 [datasheet] 8153f?avr?08/2013 8. memories 8.1 features ? flash program memory ? one linear address space ? in-system programmable ? self-programming and boot loader support ? application section for application code ? application table section for application code or data storage ? boot section for application code or bootloader code ? separate read/write protection lock bits for all sections ? built in fast crc check of a select able flash program memory section ? data memory ? one linear address space ? single-cycle access from cpu ? sram ? eeprom ? byte and page accessible ? memory mapped for direct load and store ? i/o memory ? configuration and status registers for all peripherals and modules ? 4 bit-accessible general purpose registers for global variables or flags ? bus arbitration ? deterministic handling of priority between cp u, edma controller, and other bus masters ? separate buses for sram, eeprom and i/o memory ? simultaneous bus access for cpu and edma controller ? production signature row memory for factory programmed data ? id for each microcontroller device type ? serial number for each device ? calibration bytes for fact ory calibrated peripherals ? user signature row ? one flash page in size ? can be read and written from software ? content is kept after chip erase 8.2 overview the atmel avr architecture has two main memory spaces, the program memory and the data memory. executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. the data memory includes the internal sram, and eeprom for nonvol atile data storage. all memory spaces are linear and require no memory bank switching. nonvolatile memory (n vm) spaces can be locked for further write and read/write operations. this prevents unrestricted access to the application software. a separate memory section contains the fuse bytes. these are used for configuring important system functions, and can only be written by an external programmer. the available memory size configurations are shown in ?ordering information? on page 2? . in addition, each device has a flash memory signature row for calibration data, device identification, serial number etc.
11 xmega e5 [datasheet] 8153f?avr?08/2013 8.3 flash program memory the atmel ? avr ? xmega ? devices contain on-chip, in-system reprogrammable flash memory for program storage. the flash memory can be accessed for read and write from an ex ternal programmer through the pdi or from application software running in the device. all avr cpu instructions are 16 or 32 bits wide, and each flas h location is 16 bits wide. the flash memory is organized in two main sections, the application section and the boot loader section. the sizes of the different sections are fixed, but device-dependent. these two sections have separate lock bits, and can have different levels of protection. the store program memory (spm) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. the application section contains an application table section with separate lock settings. this enables safe storage of nonvolatile data in the program memory. figure 8-1. flash program memory (hexadecimal address). 8.3.1 application section the application section is the section of the flash that is used for storing the executable application code. the protection level for the application section can be selected by the boot lock bits for this section. the application section can not store any boot loader code since the spm instruction cannot be executed from the application section. 8.3.2 application table section the application table section is a part of the application sect ion of the flash memory that can be used for storing data. the size is identical to the boot loader section. the protection level for the application table section can be selected by the boot lock bits for this section. the possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. if this section is not used for data, application code can reside here. 8.3.3 boot loader section while the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the spm instruction can only initia te programming when executing from this section. when programming, the cpu is halted, waiting for the flash operation to complete. the spm instruction can access the entire flash, including the boot loader section itself. the protection level for the boot loader section can be selected by the boot loader lock bits. if this section is not used for boot loader software, application code can be stored here. word address atxmega32e5 atxmega16e5 atxmega8e5 000 application section (32k/16k/8k) ... 37ff / 17ff / bff 3800 / 1800 / c00 application table section (4k/4k/2k) 3fff / 1fff / fff 4000 / 2000 / 1000 boot section (4k/4k/2k) 47ff / 27ff / 13ff
12 xmega e5 [datasheet] 8153f?avr?08/2013 8.3.4 production signature row the production signature row is a separate memory section for factory programmed data. it contains calibration data for functions such as oscillators and analog modules. some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. other va lues must be loaded from the signature row and written to the corresponding peripheral registers from software . for details on calibration conditions, refer to ?electrical characteristics? on page 71 . the production signature row also contains an id that identif ies each microcontroller device type and a serial number for each manufactured device. the serial number consists of the production lot number, wafer number, and wafer coordinates for the device. the device id for the available devices is shown in table 8-1 . the production signature row cannot be written or erased, but it can be read from application software and external programmers. table 8-1. device id bytes for atmel avr xmega e5 devices. 8.3.5 user signature row the user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. it is one flash page in size, and is mean t for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. this section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. this ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 8.4 fuses and lock bits the fuses are used to configure important system functions , and can only be written from an external programmer. the application software can read the fuses. the fuses are used to configure reset sources such as brownout detector and watchdog, startup configuration, etc. the lock bits are used to set protection levels for the differ ent flash sections (i.e., if read and/or write access should be blocked). lock bits can be written by external programmers and application software, but only to stricter protection levels. chip erase is the only way to erase the lock bits. to ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. an un-programmed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. both fuses and lock bits are reprogrammable like the flash program memory. 8.5 data memory the data memory contains the i/o memory, internal sram and eeprom. the data memory is organized as one continuous memory section, see table 8-2 on page 14 . to simplify development, i/o memory, eeprom and sram will always have the same start addresses for all xmega devices. device device id bytes byte 2 byte 1 byte 0 atxmega32e5 4c 95 1e atxmega16e5 45 94 1e atxmega8e5 41 93 1e
13 xmega e5 [datasheet] 8153f?avr?08/2013 figure 8-2. data memory map (hexadecimal value) 8.6 eeprom atmel avr xmega e5 devices have eeprom for nonvolatile data storage. it is memory mapped and accessed in normal data space. the eeprom supports both byte and page access. eeprom allows highly efficient eeprom reading and eeprom buffer loading. when doing this, eeprom is accessible using load and store instructions. eeprom will always start at hexadecimal address 0x1000. 8.7 i/o memory the status and configuration registers for peripherals and modules, including the cpu, are addressable through i/o memory locations. all i/o locations can be accessed by the load (ld/lds/ldd) and store (st/sts/std) instructions, which are used to transfer data between the 32 registers in the register file and the i/o memory. the in and out instructions can address i/o memory locations in the range of 0x00 to 0x3f directly. in the address range 0x00 - 0x1f, single-cycle instructions for manipulation and c hecking of individual bits are available. the i/o memory address for all peripherals and modules in xmega e5 is shown in the ?peripheral module address map? on page 61 . 8.7.1 general purpose i/o registers the lowest 4 i/o memory addresses are reserved as general purpose i/o registers. these registers can be used for storing global variables and flags, as they are directly bit- accessible using the sbi, cbi, sbis, and sbic instructions. 8.8 data memory and bus arbitration since the data memory is organized as three separate sets of memories, the different bus masters (cpu, edma controller read and edma controller write, etc.) can access different memory sections at the same time. 8.9 memory timing read and write access to the i/o memory takes one cpu clock cycle. a write to sram takes one cycle, and a read from sram takes two cycles. for burst read (edma), new data ar e available every cycle. eeprom page load (write) takes one cycle, and three cycles are required for read. for burst r ead, new data are available every second cycle. refer to the instruction summary for more details on instructions and instruction timing. 8.10 device id and revision each device has a three-byte device id. this id identifies atmel as the manufacturer of the device and the device type. a separate register contains the revision number of the device. byte address atxmega32e5 byte address atxmega16e5 byte address atxmega8e5 0 i/o registers (4k) 0 i/o registers (4k) 0 i/o registers (4k) fff fff fff 1000 eeprom (1k) 1000 eeprom (512b) 1000 eeprom (512b) 13ff 11ff 11ff reserved reserved reserved 2000 internal sram (4k) 2000 internal sram (2k) 2000 internal sram (2k) 2fff 27ff 27ff
14 xmega e5 [datasheet] 8153f?avr?08/2013 8.11 i/o memory protection some features in the device are regarded as critical for safety in some applications. due to this, it is possible to lock the i/o register related to the clock system, the event system, and the waveform extensions. as long as the lock is enabled, all related i/o registers are locked and they cannot be wri tten from the application software. the lock registers themselves are protected by the configuration change protection mechanism. 8.12 flash and eeprom page size the flash program memory and eeprom data memory are or ganized in pages. the pages are word accessible for the flash and byte accessible for the eeprom. table 8-2 shows the flash program memory organization and program counter (p c) size. flash write and erase operations are performed on one page at a time, while reading the flash is done one byte at a time. for flash access the z-pointer (z[m:n]) is used for addressing. the most signifi cant bits in the address (fpage) give the page number and the least significant address bits (fword) give the word in the page. table 8-2. number of words and pages in the flash. table 8-3 shows eeprom memory organization for the atmel avr xmega e5 devices. eeprom write and erase operations can be performed one page or one byte at a time, while reading the eeprom is done one byte at a time. for eeprom access the nvm address register (addr[m:n]) is used for addressing. the most significant bits in the address (e2page) give the page number and the least significant address bits (e2byte) give the byte in the page. table 8-3. number of word s and pages in the eeprom. devices pc size flash size page size fword fpage application boot bits bytes words size no of pages size no of pages atxmega32e5 15 32k+4k 64 z[6:0] z[14:7] 32k 256 4k 32 atxmega16e5 14 16k+4k 64 z[6:0] z[13:7] 16k 128 4k 32 atxmega8e5 13 8k+2k 64 z[6:0] z[12:7] 8k 64 2k 16 devices eeprom page size e2byte e2page no of pages size bytes atxmega32e5 1k 32 addr[4:0] addr[10:5] 32 atxmega16e5 512bytes 32 addr[4:0] addr[10:5] 16 atxmega8e5 512bytes 32 addr[4:0] addr[10:5] 16
15 xmega e5 [datasheet] 8153f?avr?08/2013 9. edma ? enhanced dma controller 9.1 features ? the edma controller allows data transfers with minimal cpu intervention ? from data memory to data memory ? from data memory to peripheral ? from peripheral to data memory ? from peripheral to peripheral ? four peripheral edma channels with separate: ? transfer triggers ? interrupt vectors ? addressing modes ? data matching ? two peripheral channels can be combined to one standard channel with separate: ? transfer triggers ? interrupt vectors ? addressing modes ? data search ? programmable channel priority ? from 1byte to 128kb of data in a single transaction ? up to 64k block transfer with repeat ? 1 or 2 bytes burst transfers ? multiple addressing modes ? static ? increment ? optional reload of source and destination address at the end of each ? burst ? block ? transaction ? optional interrupt on end of transaction ? optional connection to crc generator module for crc on edma data 9.2 overview the four-channel enhanced direct memory access (edma) controller can transfer data between memories and peripherals, and thus offload these tasks from the cpu. it enables high data transfer rates with minimum cpu intervention, and frees up cpu time. the four edma channels enable up to four independent and parallel transfers. the edma controller can move data between sram and peri pherals, between sram locations and directly between peripheral registers. with access to all peripherals, the edma controller can handle automatic transfer of data to/from communication modules. the edma controller can also read from eeprom memory. data transfers are done in continuous bursts of 1 or 2 bytes. they build block transfers of configurable size from 1 byte to 64kb. repeat option can be used to repeat once each block transfer for single transactions up to 128kb. source and destination addressing can be static or incremental. auto matic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transacti on is complete. application software, peripherals, and events can trigger edma transfers. the four edma channels have individual configuration and contro l settings. this includes source, destination, transfer triggers, and transaction sizes. they have individual in terrupt settings. interrupt requests can be generated when a transaction is complete or when the edma controller detects an error on an edma channel.
16 xmega e5 [datasheet] 8153f?avr?08/2013 to enable flexibility in transfers, channels can be interlinked so that the second takes over the transfer when the first is finished. the edma controller supports extended features such as double buffering, data match for peripherals and data search for sram or eeprom. the edma controller supports two types of channel. each channel type can be selected individually.
17 xmega e5 [datasheet] 8153f?avr?08/2013 10. event system 10.1 features ? system for direct peripheral-to- peripheral communication and signaling ? peripherals can directly send, receive, and react to peripheral events ? cpu and edma controller independent operation ? 100% predictable signal timing ? short and guaranteed response time ? synchronous and asynch ronous event routing ? eight event channels for up to eight different and parallel signal routing and configurations ? events can be sent and/or used by most peripherals, clock system, and software ? additional functions include ? quadrature decoder with rotary filtering ? digital filtering of i/o pin state with configurable filter ? simultaneous synchronous and asynchronous events provided to peripheral ? works in all sleep modes 10.2 overview the event system enables direct peripheral-to-peripheral communication and signaling. it allows a change in one peripheral?s state to automatically trigger actions in other peripherals. it is designed to provide a predictable system for short and predictable response times between peripherals. it allows for autonomous peripheral control and interaction without the use of interrupts, cpu, or edma controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. it allows for syn chronized timing of actions in several peripheral modules. the event system enables also asynchronous event routing for instant actions in peripherals. a change in a peripheral?s state is referred to as an event, and usually corresponds to the peripheral?s interrupt conditions. events can be directly passed to other peripherals using a dedicated routing network called the event routing network. how events are routed and used by the peripherals is configured in software. figure 10-1 shows a basic diagram of all connected peripherals. the event system can directly connect together analog and digital converters, analog comparators, i/o port pins, the real-time counter, timer/counters, ir communication module (ircom) and xmega custom logic (programmable logic) block (xcl). it can also be used to trigger edma transactions (edma controller). events can also be generated from software and peripheral clock.
18 xmega e5 [datasheet] 8153f?avr?08/2013 figure 10-1. event system overview and connected peripherals. the event routing network consists of eight software-configurable multiplexers that control how events are routed and used. these are called event channels, and allow up to eight parallel event configurations and routing. the maximum routing latency of an external event is two peripheral clo ck cycles due to re-synchronization, but several peripherals can directly use the asynchronous event without any clock delay. the event system works in all power sleep modes, but only asynchronous events can be routed in sleep modes where the system clock is not available. timer / counters adc real time counter cpu / software edma controller ircom event routing network event system controller clk per prescaler ac port pins dac xmega custom logic
19 xmega e5 [datasheet] 8153f?avr?08/2013 11. system clock and clock options 11.1 features ? fast start-up time ? safe run-time clock switching ? internal oscillators: ? 32mhz run-time calibrated and tuneable oscillator ? 8mhz calibrated oscillator with 2m hz output option and fast start-up ? 32.768khz calibrated oscillator ? 32khz ultra low power (ulp) oscillator with 1khz output ? external clock options ? 0.4 - 16mhz crystal oscillator ? 32khz crystal oscillator with digital correction ? external clock input in selectable pin location ? pll with 20 - 128mhz output frequency ? internal and external clock options and 1 to 31x multiplication ? lock detector ? clock prescalers with 1x to 2048x division ? fast peripheral clocks running at 2 and 4 times the cpu clock frequency ? automatic run-time calibration of the 32mhz internal oscillator ? external oscillator and pll lock failure detection with optional non maskable interrupt 11.2 overview atmel avr xmega e5 devices have a flexible clock system s upporting a large number of clock sources. it incorporates both accurate internal oscillators and external crysta l oscillator and resonator support. a high-frequency phase locked loop (pll) and clock prescalers can be used to generate a wide range of clock frequencies. a calibration feature (dfll) is available, and can be used for automatic run-time calibrati on of the 32mhz internal oscill ator to remove frequency drift over voltage and temperature. an oscillator failure monitor can be enabled to issue a nonmaskable interrupt and switch to the internal oscillator if the external oscillator or pll fails. when a reset occurs, all clock sources except the 32khz ultra low power oscillator are disabled. after reset, the device will always start up running from the 2mhz output of the 8mhz internal oscillator. during normal operation, the system clock source and prescalers can be changed from software at any time. figure 11-1 presents the principal clock system in the xmega e5 family of devices. not all of the clocks need to be active at a given time. the clocks for the cpu and per ipherals can be stopped using sleep modes and power reduction registers, as described in ?power management and sleep modes? on page 22 .
20 xmega e5 [datasheet] 8153f?avr?08/2013 figure 11-1. the clock system, clo ck sources and clock distribution. 11.3 clock sources the clock sources are divided in two main groups: internal oscillators and external clock sources. most of the clock sources can be directly enabled and disabled from softwa re, while others are automatically enabled or disabled, depending on peripheral settings. after reset, the device starts up running from the 2mhz output of the 8mhz internal oscillator. the other clock sources, dfll and pll, are turned off by default. the internal oscillators do not require any external component s to run. for details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. 11.3.1 32khz ultra low power internal oscillator this oscillator provides an approximate 32khz clock. the 32khz ultra low power (ulp) internal oscillator is a very low power clock source, and it is not designed for high accuracy. the oscillator employs a built-in prescaler that provides a real time counter peripherals ram avr cpu non-volatile memory watchdog timer brown-out detector system clock prescalers system clock multiplexer (sclksel) div32 32 khz int. ulp 32.768 khz int. osc 32.768 khz tosc 8mhz int. osc 32 mhz int. osc 0.4 C 16 mhz xtal div32 div32 div4 pll tosc1 tosc2 xtal1 xtal2 clk sys clk rtc clk per2 clk per clk cpu clk per4 pc[4] xoscsel rtcsrc pllsrc div4
21 xmega e5 [datasheet] 8153f?avr?08/2013 1khz output. the oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. this oscillator can be selected as the clock source for the rtc. 11.3.2 32.768khz calibrate d internal oscillator this oscillator provides an approximate 32.768khz clock. it is calibrated during production to provide a default frequency close to its nominal frequency. the calibration register can also be written from software for run-time calibration of the oscillator frequency. the oscillator employs a built-in pre scaler, which provides both a 32.768khz output and a 1.024khz output. 11.3.3 32.768khz crystal oscillator a 32.768khz crystal oscillator can be connected between the tosc1 and tosc2 pins and enables a dedicated low frequency oscillator input circuit. a low power mode with reduc ed voltage swing on tosc2 is available. this oscillator can be used as a clock source for the system clock and rtc, and as the dfll reference clock. 11.3.4 0.4 - 16mhz crystal oscillator this oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16mhz. 11.3.5 8mhz calibrated internal oscillator the 8mhz calibrated internal oscillator is the default system clock source after reset. it is calibrated during production to provide a default frequency close to its nominal frequency. the ca libration register can also be written from software for run-time calibration of the oscillator frequency. the oscillator employs a built-in prescaler, with 2mhz output. the default output frequency at start-up and after reset is 2mhz. a low power mode option can be used to enable fast system wake- up from power-save mode. in all other modes, the low power mode can be enabled to significantly reduce the power consumption of the internal oscillator. 11.3.6 32mhz run-time calib rated internal oscillator the 32mhz run-time calibrated internal oscillator is a high-frequency oscillator. it is calibrated during production to provide a default frequency close to its nominal frequency. a digital frequency looked loop (dfll) can be enabled for automatic run-time calibration of the oscillator to compens ate for temperature and voltage drift and optimize the oscillator accuracy. this oscillator can also be adjusted and calibrated to any frequency between 30mhz and 55mhz. 11.3.7 external clock sources the xtal1 and xtal2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. xtal1 or pin 4 of port c (pc4) can be used as input fo r an external clock signal. the tosc1 and tosc2 pins are dedicated to driving a 32.768khz crystal oscillator. 11.3.8 pll with 1x-31x multiplication factor the built-in phase locked loop (pll) can be used to generat e a high-frequency system clock. the pll has a user- selectable multiplication factor of from 1 to 31. in combin ation with the prescalers, this gives a wide range of output frequencies from all clock sources.
22 xmega e5 [datasheet] 8153f?avr?08/2013 12. power management and sleep modes 12.1 features ? power management for adjusting power consumption and functions ? five sleep modes ? idle ? power down ? power save ? standby ? extended standby ? power reduction register to disable clock and turn off unused peripherals in active and idle modes 12.2 overview various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. this enables the atmel avr xmega microcontroller to stop unused modules to save power. all sleep modes are available and can be entered from active mode. in active mode, the cpu is executing application code. when the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. the application code decides which sleep m ode to enter and when. interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. in addition, power reduction registers provide a method to st op the clock to individual peripherals from software. when this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. this reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 12.3 sleep modes sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. xmega microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. a dedicated sleep instruction (sleep) is avail able to enter sleep mode. interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. when an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the sleep instruction. if other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. after wake-up, the cpu is halted for four cycles before execution starts. the content of the register file, sram and registers are kept during sleep. if a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 12.3.1 idle mode in idle mode the cpu and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and edma controller are kept running. any enabled interrupt will wake the device. 12.3.2 power-down mode in power-down mode, all clocks, including the real-time count er clock source, are stopped. this allows operation only of asynchronous modules that do not require a running clock. the only interrupts that can wake up the mcu are the two- wire interface address match interrupt and asynchronous port interrupts.
23 xmega e5 [datasheet] 8153f?avr?08/2013 12.3.3 power-save mode power-save mode is identical to power down, with one excepti on. if the real-time counter (rtc) is enabled, it will keep running during sleep, and the device can also wake up from either an rtc overflow or compare match interrupt. low power mode option of 8mhz internal oscillator enables instant oscillator wake-up time. this reduces the mcu wake-up time or enables the mcu wa ke-up from uart bus. 12.3.4 standby mode standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the cpu, peripheral, and rtc clocks are stopped. this reduces the wake-up time. the low power option of 8mhz internal oscillator can be enabled to further reduce the power consumption. 12.3.5 extended standby mode extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the cpu and peripheral clocks are stopped. this reduces the wake-up time. the low power option of 8mhz internal oscillator can be enabled to further reduce the power consumption.
24 xmega e5 [datasheet] 8153f?avr?08/2013 13. system control and reset 13.1 features ? reset the microcontroller and set it to initial state when a reset source goes active ? multiple reset sources that cover different situations ? power-on reset ? external reset ? watchdog reset ? brownout reset ? pdi reset ? software reset ? asynchronous operation ? no running system clock in the device is required for reset ? reset status register for reading the reset source from the application code 13.2 overview the reset system issues a microcontroller reset and sets the device to its initial state. this is for situations where operation should not start or continue, such as when the micr ocontroller operates below its power supply rating. if a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. the i/o pins are immediately tri-stated. the program counter is set to the reset vector location, and all i/o registers are set to their initial values. the sram content is kept. however, if the device accesses the sram when a reset occurs, the content of the accessed location can not be guaranteed. after reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. by default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. the reset functionality is asynchronous, and so no running syst em clock is required to reset the device. the software reset feature makes it possible to issue a controlled system reset from the user software. the reset status register has individual status flags fo r each reset source. it is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. 13.3 reset sequence a reset request from any reset source will immediately rese t the device and keep it in reset as long as the request is active. when all reset requests are released, the device will go through three stages before the device starts running again: ? reset counter delay ? oscillator startup ? oscillator calibration if another reset requests occurs during this process, the reset sequence will start over again. 13.4 reset sources 13.4.1 power-on reset a power-on reset (por) is generated by an on-chip detection circuit. the por is activated when the v cc rises and reaches the por threshold voltage (v pot ), and this will start the reset sequence. the por is also activated to power down the device properly when the v cc falls and drops below the v pot level. the v pot level is higher for falling v cc than for rising v cc . consult the datasheet for por characteristics data.
25 xmega e5 [datasheet] 8153f?avr?08/2013 13.4.2 brownout detection the on-chip brownout detection (bod) circuit monitors the v cc level during operation by comparing it to a fixed, programmable level that is selected by the bodlevel fuses. if disabled, bod is forced on at the lowest level during chip erase and when the pdi is enabled. 13.4.3 external reset the external reset circuit is connected to the external reset pin. the external reset will trigger when the reset pin is driven below the reset pin threshold voltage, v rst , for longer than the minimum pulse period, t ext . the reset will be held as long as the pin is kept low. the reset pin includes an internal pull-up resistor. 13.4.4 watchdog reset the watchdog timer (wdt) is a system function for monitoring correct program operation. if the wdt is not reset from the software within a programmable timeout period, a watchdog reset will be given. the watchdog reset is active for one to two clock cycles of the 2mhz internal oscillator. for more details see ?wdt ? watchdog timer? on page 26 . 13.4.5 software reset the software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register. the reset will be issued within two cpu clock cycles after writing the bit. it is not possible to execute any instruction from when a software reset is requested until it is issued. 13.4.6 program and debug interface reset the program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. this reset source is acce ssible only from external debuggers and programmers.
26 xmega e5 [datasheet] 8153f?avr?08/2013 14. wdt ? watchdog timer 14.1 features ? issues a device reset if the timer is not reset before its timeout period ? asynchronous operation from dedicated oscillator ? 1khz output of the 32khz ultra low power oscillator ? 11 selectable timeout periods, from 8ms to 8s ? two operation modes: ? normal mode ? window mode ? configuration lock to prevent unwanted changes 14.2 overview the watchdog timer (wdt) is a system function for monitoring correct program operation. it makes it possible to recover from error situations such as runaway or deadlocked code. the wdt is a timer, configured to a predefined timeout period, and is constantly running when enabled. if the wdt is not reset within the timeout period, it will issue a microcontroller reset. the wdt is reset by executing the wdr (watchdog timer reset) instruction from the application code. the window mode makes it possible to define a time slot or window inside the total timeout period during which wdt must be reset. if the wdt is reset outside this window, either too early or too late, a system reset will be issued. compared to the normal mode, this can also catch situat ions where a code error causes constant wdr execution. the wdt will run in active mode and all sleep modes, if e nabled. it is asynchronous, runs from a cpu-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. the configuration change protection mechanism ensures that the wdt settings cannot be changed by accident. for increased safety, a fuse for locking the wdt settings is also available.
27 xmega e5 [datasheet] 8153f?avr?08/2013 15. interrupts and programmable multilevel interrupt controller 15.1 features ? short and predictable interrupt response time ? separate interrupt configuration and vector address for each interrupt ? programmable multilevel interrupt controller ? interrupt prioritizing according to level and vector address ? three selectable interrupt levels for all interrupts: low, medium and high ? selectable, round-robin priority scheme within low-level interrupts ? non-maskable interrupts for critical functions ? interrupt vectors optionally placed in the application section or the boot loader section 15.2 overview interrupts signal a change of state in peripherals, and this c an be used to alter program execution. peripherals can have one or more interrupts, and all are individually enabled and configured. when an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. the programmable multilevel interrupt controller (pmic) controls the handling and prioritizing of interrupt requests. when an interrupt request is acknowledged by the pmic, the program counter is set to point to t he interrupt vector, and the interrupt handler can be executed. all peripherals can select between three different priority leve ls for their interrupts: low, medium, and high. interrupts are prioritized according to their level and their interrupt vect or address. medium-level interrupts will interrupt low-level interrupt handlers. high-level interrupts wil l interrupt both medium- and low-level interrupt handlers. within each level, the interrupt priority is decided from the interrupt vector addres s, where the lowest interrupt vector address has the highest interrupt priority. low-level interrupts have an optional r ound-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. non-maskable interrupts (nmi) are also supported, and can be used for system critical functions. 15.3 interrupt vectors the interrupt vector is the sum of the peripheral?s base interrupt address and the offset address for specific interrupts in each peripheral. the base addresses for the atmel avr xmega e5 devices are shown in table 15-1 . offset addresses for each interrupt available in the peripheral are described for each peripheral in the xmega au manual. for peripherals or modules that have only one interrupt, the interrupt vector is shown in table 15-1 . the program address is the word address. table 15-1. peripheral module address map program address (base address) source interrupt description 0x0000 reset 0x0002 oscf_int_vect crystal oscillator failure and pll lock failure interrupt vector (nmi) 0x0004 portr_int_vect port r interrupt vector 0x0006 edma_int_base edma controller interrupt base 0x000e rtc_int_base real time counter interrupt base 0x0012 portc_int_vect port c interrupt vector 0x0014 twic_int_base two-wire interface on port c interrupt base
28 xmega e5 [datasheet] 8153f?avr?08/2013 0x0018 tcc4_int_base timer/counter 4 on port c interrupt base 0x0024 tcc5_int_base timer/counter 5 on port c interrupt base 0x002c spic_int_vect spi on port c interrupt vector 0x002e usartc0_int_base usart 0 on port c interrupt base 0x0034 nvm_int_base non-volatile memory interrupt base 0x0038 xcl_int_base xcl (programmable logic) module interrupt base 0x003c porta_int_vect port a interrupt vector 0x003e aca_int_base analog comparator on port a interrupt base 0x0044 adca_int_base analog to digital converter on port a interrupt base 0x0046 portd_int_vect port d interrupt vector 0x0048 tcd5_int_base timer/counter 5 on port d interrupt base 0x0050 usartd0_int_base usart 0 on port d interrupt base program address (base address) source interrupt description
29 xmega e5 [datasheet] 8153f?avr?08/2013 16. i/o ports 16.1 features ? 26 general purpose input and output pins with individual configuration ? output driver with configurable driver and pull settings: ? totem-pole ? wired-and ? wired-or ? bus-keeper ? inverted i/o ? input with asynchronous sensing with interrupts and events ? sense both edges ? sense rising edges ? sense falling edges ? sense low level ? optional pull-up and pull-down resistor on input and wired-or/and configurations ? optional slew rate control per i/o port ? asynchronous pin change sensing that can wake the device from all sleep modes ? one port interrupt with pin masking per i/o port ? efficient and safe access to port pins ? hardware read-modify-write through de dicated toggle/clear/set registers ? configuration of multiple pins in a single operation ? mapping of port registers into bit-accessible i/o memory space ? peripheral clocks output on port pin ? real-time counter clock output to port pin ? event channels can be output on port pin ? remapping of digital peripheral pin functions ? selectable usart and timer/counters input/output pin locations ? selectable analog comparator output pin locations 16.2 overview one port consists of up to 8 pins ranging from pin 0 to 7. each port pin can be configured as input or output with configurable driver and pull settings. they also implement asynchronous input sensing with interrupt and events for selectable pin change conditions. asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, including the modes where no clocks are running. all functions are individual and configurable per pin, but se veral pins can be configured in a single operation. the pins have hardware read-modify-write (rmw) functionality for safe and correct change of drive value and/or pull resistor configuration. the direction of one port pin can be changed without unintentionally changing the direction of any other pin. the port pin configuration also controls input and output selection of other device functions. it is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. the same applies to events from the event system that can be used to synchronize and cont rol external functions. other digital peripherals, such as usart, timer/counters, and analog comparator output can be remapped to selectable pin locations in order to optimize pin-out versus application needs. the notations of the ports are porta, portc, portd, and portr.
30 xmega e5 [datasheet] 8153f?avr?08/2013 16.3 output driver all port pins (pxn) have programmable output configuration. t he port pins also have configurable slew rate limitation to reduce electromagnetic emission. 16.3.1 push-pull figure 16-1. i/o configuration - totem-pole. 16.3.2 pull-down figure 16-2. i/o configuration - totem-pole with pull-down (on input). 16.3.3 pull-up figure 16-3. i/o configuration - totem-pole with pull-up (on input). inxn outxn dirxn pxn inxn outxn dirxn pxn inxn outxn dirxn pxn
31 xmega e5 [datasheet] 8153f?avr?08/2013 16.3.4 bus-keeper the bus-keeper?s weak output produces the same logical level as the last output level. it acts as a pull-up if the last level was ?1?, and pull-down if the last level was ?0?. figure 16-4. i/o configuration - totem-pole with bus-keeper. 16.3.5 others figure 16-5. output configuration - wired-or with optional pull-down. figure 16-6. i/o conf iguration - wired-and wi th optional pull-up. inxn outxn dirxn pxn inxn outxn pxn inxn outxn pxn
32 xmega e5 [datasheet] 8153f?avr?08/2013 16.4 input sensing input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in figure 16-7 . figure 16-7. input sensing system overview. when a pin is configured with inverted i/o, the pin value is inverted before the input sensing. 16.5 alternate port functions most port pins have alternate pin functions in addition to being a general purpose i/o pin. when an alternate function is enabled, it might override the normal port pin function or pin va lue. this happens when other per ipherals that require pins are enabled or configured to use pins. if and how a peripheral will override and use pins is described in the section for that peripheral. ?pinout and pin functions? on page 57 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. d q r inverted i/o interrupt control d q r pxn synchronizer inn edge detect synchronous sensing edge detect asynchronous sensing irq synchronous events asynchronous events
33 xmega e5 [datasheet] 8153f?avr?08/2013 17. timer counter type 4 and 5 17.1 features ? three 16-bit timer/counter ? one timer/counter of type 4 ? two timer/counter of type 5 ? 32-bit timer/counter support by cascading two timer/counters ? up to four compare or capture (cc) channels ? four cc channels for ti mer/counters of type 4 ? two cc channels for timer/counters of type 5 ? double buffered timer period setting ? double buffered cc channels ? waveform generation modes: ? frequency generation ? single-slope pulse width modulation ? dual-slope pulse width modulation ? input capture: ? input capture with noise cancelling ? frequency capture ? pulse width capture ? 32-bit input capture ? timer overflow and error interrupts/events ? one compare match or input capture interrupt/event per cc channel ? can be used with event system for: ? quadrature decoding ? count and direction control ? input capture ? can be used with edma and to trigger edma transactions ? high-resolution extension ? increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit) ? waveform extension ? low- and high-side output with pr ogrammable dead-time insertion (dti) ? fault extention ? event controlled fault protection for safe disabling of drivers 17.2 overview atmel avr xmega devices have a set of flexible, 16-bit time r/counters (tc). their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit input capture. a timer/counter consists of a base counter and a set of compare or capture (cc) channels. the base counter can be used to count clock cycles or events. it has direction control and period setting that can be used for timing. the cc channels can be used together with the base counter to do compare match control, frequency generation, and pulse width modulation (pwm) generation, as well as various input capture operations. a timer/counter can be configured for either capture, compare, or capture and compare function. a timer/counter can be clocked and timed from the peripheral clock with optional prescaling, or from the event system. the event system can also be used for direction control, input capture trigger or to synchronize operations.
34 xmega e5 [datasheet] 8153f?avr?08/2013 there are two differences between timer/counter type 4 and type 5. timer/counter 4 has four cc channels, and timer/counter 5 has two cc channels. both timer/counter 4 and 5 can be set in 8-bit mode, allowing the application to double the number of compare and capture channels that then get 8-bit resolution. some timer/counters have extensions that enable more specialized waveform generation. the waveform extension (wex) is intended for motor control, ballast, led, h-bri dge, power converters, and other types of power control applications. it enables more customized waveform output distribution, and low- and high-side channel output with optional dead-time insertion. it can also generate a synchronized bit pattern across the port pins. the high-resolution (hi- res) extension can increase the waveform resolution by four or eight times by using an internal clock source four times faster than the peripheral clock. the fault extension (fault ) enables fault protection for safe and deterministic handling, disabling and/or shut down of external drivers. a block diagram of the 16-bit timer/counter with extensions and closely related peripheral modules (in grey) is shown in figure 17-1 . figure 17-1. 16-bit ti mer/counter and closel y related peripherals. portc has one timer/counter 4 and one timer/counter 5. port d has one timer/counter 5. notation of these are tcc4 (timer/counter c4), tcc5 and tcd5 respectively. compare/capture channel d compare/capture channel c compare/capture channel b compare/capture channel a waveform generation buffer comparator capture control base counter counter control logic timer period prescaler event system timer/counter clk per4 clk per wex
35 xmega e5 [datasheet] 8153f?avr?08/2013 18. wex ? waveform extension 18.1 features ? module for more customized and advanced waveform generation ? optimized for various type of motor, ballast, and power stage control ? output matrix for timer/counter waveform output distribution ? configurable distribution of compare channel output across port pins ? redistribution of dead-time insertion resource between tc4 and tc5. ? four dead-time insertion (dti) units, each with ? complementary high and low side with non overlapping outputs ? separate dead-time setting for high and low side ? 8-bit resolution ? four swap (swap) units ? separate port pair or low high side drivers swap ? double buffered swap feature ? pattern generation creating synchronized bit pattern across the port pins ? double buffered pattern generation 18.2 overview the waveform extension (wex) provides extra functions to the timer/counter in waveform generation (wg) modes. it is primarily intended for motor control, ballast, led, h-bri dge, power converters, and other types of power control applications. the wex consist of five independent and successive units, as shown in figure 18-1 . figure 18-1. waveform extension and closely related peripherals. the output matrix (otmx) can distribute and route out the waveform outputs from timer/counter 4 and 5 across the port pins in different configurations, each optimized for different application types. the dead time insertion (dti) unit splits the four lower otmx outputs into a two non-overlapping signals , the non-inverted low side (ls) and inverted high side (hs) of the waveform output with optional dead-time insertion between ls and hs switching. swap1 dti1 swap1 dti1 swap1 dti1 swap1 dti1 pattern generator output matrix wex px7 px6 px5 px4 px3 px2 px1 px0 fault unit 5 fault unit 4 t/c4 t/c5 outovdis hires
36 xmega e5 [datasheet] 8153f?avr?08/2013 the swap (swap) unit can swap the ls and hs pin position. this can be used for fast decay motor control. the pattern generation unit generates synchronized output waveform with constant logic level. this can be used for easy stepper motor and full bridge control. the output override disable unit can disable the waveform output on selectable port pins to optimize the pins usage. this is to free the pins for other functional use, when the application does not need the waveform output spread across all the port pins as they can be selected by the otmx configurations. the waveform extension is available for tcc4 and tcc5. the notation of this is wexc.
37 xmega e5 [datasheet] 8153f?avr?08/2013 19. hi-res ? high r esolution extension 19.1 features ? increases waveform generator resolution up to 8x (three bits) ? supports frequency, single-slope pwm, and dual-slope pwm generation ? supports the wex when this is used for the same timer/counter 19.2 overview the high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. it can be used for a time r/counter doing frequency, single-slope pwm, or dual-slope pwm generation. it can also be used with the wex if this is used for the same timer/counter. the hi-res extension uses the peripheral 4x clock (clkper4). the system clock prescalers must be configured so the peripheral 4x clock frequency is four times higher than t he peripheral and cpu clock frequency when the hi-res extension is enabled. there is one hi-res extension that can be enabled for timer/counters pair on portc. the notation of this is hiresc.
38 xmega e5 [datasheet] 8153f?avr?08/2013 20. fault extension 20.1 features ? connected to timer/counter output and waveform extension input ? event controlled fault protection for instant and predictable fault triggering ? fast, synchronous and asynchronous fault triggering ? flexible configuration with multiple fault sources ? recoverable fault modes ? restart or halt the timer/ counter on fault condition ? timer/counter input capture on fault condition ? waveform output active time reduction on fault condition ? non-recoverable faults ? waveform output is forced to a pre-configured safe state on fault condition ? optional fuse output value configuration defi ning the output state during system reset ? flexible fault filter selections ? digital filter to prevent false triggers from i/o pin glitches ? fault blanking to prevent false triggers during commutation ? fault input qualification to filter the fault input during the inactive output compare states 20.2 overview the fault extension enables event controlled fault protection by acting directly on the generated waveforms from timer/counter compare outputs. it can be used to trigger two types of faults with the following actions: ? recoverable faults: the timer/counter can be restarted or halted as long as the fault condition is preset. the compare output pulse active time can be reduced as long as the fault condition is preset. this is typically used for current sensing regulation, zero crossing re-t riggering, demagnetization re-triggering, and so on. ? non-recoverable faults: the compare outputs are forced to a safe and pre-configured values that are safe for the application. this is typically used for instant and predict able shut down and to disable the high current or voltage drivers. events are used to trigger a fault condition. one or several simultaneous events are supported, both synchronously or asynchronously. by default, the fault extension supports asynchronous event operation, ensuring predictable and instant fault reaction, including system power modes where the system clock is stopped. by using the input blanking, the fault input qualification or digital filter option in event system, the fault sources can be filtered to avoid false faults detection. there are two fault extensions, one for each of the timer/counter 4 and timer/counter 5 on portc. the notation of these are faultc4 and faultc5, respectively.
39 xmega e5 [datasheet] 8153f?avr?08/2013 21. rtc ? 16-bit real-time counter 21.1 features ? 16-bit resolution ? selectable clock source ? 32.768khz external crystal ? external clock ? 32.768khz internal oscillator ? 32khz internal ulp oscillator ? programmable 10-bit clock prescaling ? one compare register ? one period register ? clear counter on period overflow ? optional interrupt/event on overflow and compare match ? correction for external crystal oscillato r frequency error down to 0.5 ppm accuracy 21.2 overview the 16-bit real-time counter (rtc) is a counter that typica lly runs continuously, including in low power sleep modes, to keep track of time. it can wake up the device from sleep modes and/or interrupt the device at regular intervals. the reference clock is typically the 1.024khz output from a high-accuracy crystal of 32.768khz, and this is the configuration most optimized for low power consumption. the faster 32.768khz output can be selected if the rtc needs a resolution higher than 1ms. the rtc can also be clock ed from an external clock signal, the 32.768khz internal oscillator or the 32khz internal ulp oscillator. the rtc includes a 10-bit programmable prescaler that c an scale down the reference clock before it reaches the counter. a wide range of resolutions and time-out periods can be configured. with a 32.768khz clock source, the maximum resolution is 30.5 s, and time-out periods can range up to 2000 seconds. with a resolution of 1s, the maximum timeout period is more than 18 hours (65536 seconds). the rtc can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value.
40 xmega e5 [datasheet] 8153f?avr?08/2013 figure 21-1. real-time counter overview. the rtc also supports correction when operated using external 32.768 khz crystal oscillator. an externally calibrated value will be used for correction. the calibration can be done by measuring the default rtc frequency relative to a more accurate clock input to the device as system clock. the rtc can be calibrated to an accuracy of 0.5 ppm. the rtc correction operation will either speed up (by skipping count) or slow down (adding extra cycles) the prescaler to account for the crystal oscillator error. 32.768 khz crystal osc 32.768 khz int. osc tosc1 tosc2 external clock div32 32 khz int ulp (div32) rtcsrc clk rtc cnt per comp = = match/ compare top/ overflow calib correction counter hold count div32 10-bit prescaler
41 xmega e5 [datasheet] 8153f?avr?08/2013 22. twi ? two wire interface 22.1 features ? one two-wire interface ? phillips i 2 c compatible ? system management bus (smbus) compatible ? bus master and slave operation supported ? slave operation ? single bus master operation ? bus master in multi-master bus environment ? multi-master arbitration ? bridge mode with independent and simulta neous master and slave operation ? flexible slave address match functions ? 7-bit and general call address recognition in hardware ? 10-bit addressing supported ? address mask register for dual address match or address range masking ? optional software address recognition for unlimited number of addresses ? slave can operate in all sleep modes, including power-down ? slave address match can wake device from all sleep modes ? 100khz, 400khz and 1mhz bus frequency support ? slew-rate limited output drivers ? input filter for bus noise and spike suppression ? support arbitration between start/r epeated start and data bit (smbus) ? slave arbitration allows support for addr ess resolve protocol (arp) (smbus) ? supports smbus layer 1 timeouts ? configurable timeout values ? independent timeout counters in mast er and slave (bridge mode support) 22.2 overview the two-wire interface (twi) is a bidirectional, two-wire communication interface. it is i 2 c and system management bus (smbus) compatible. the only external hardware needed to im plement the bus is one pull-up resistor on each bus line. a device connected to the bus must act as a master or a slave. one bus can have many slaves and one or several masters that can take control of the bus. the twi module supports master and slave functionality. t he master and slave functionality are separated from each other, and can be enabled and operate simultaneously and separatel y. the master module supports multi-master bus operation and arbitration. it contains the baud rate generator. quick command and smart mode can be enabled to auto- trigger operations and reduce software complexity. the master can support 100khz, 400khz and 1mhz bus frequency. the slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. a dedicated address mask register can act as a second address match register or as a register for address range masking. the slave continues to operate in all sleep modes, including power-down mode. this enables the slave to wake up the device from all sleep modes on twi address match. it is possible to disable the address matching to let this be handled in software instead. by using the bridge option, the slave can be mapped to different pin locations. the master and slave can support 100khz, 400khz and 1mhz bus frequency. the twi module will detect start and stop conditions, bus collisions, and bus errors. arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes.
42 xmega e5 [datasheet] 8153f?avr?08/2013 it is possible to disable the twi drivers in the device, and enable a four-wire digital interface for connecting to an external twi bus driver. this can be used for applications where the device operates from a different v cc voltage than used by the twi bus. it is also possible to enable the bridge mode. in this mode, the slave i/o pins are selected from an alternative port, enabling independent and simultaneous master and slave operation. portc has one twi. notation of this peripheral is twic. al ternative twi slave location in bridge mode is on portd.
43 xmega e5 [datasheet] 8153f?avr?08/2013 23. spi ? serial pe ripheral interface 23.1 features ? one spi peripheral ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? eight programmable bit rates ? interrupt flag at the end of transmission ? write collision flag to indicate data collision ? wake up from idle sleep mode ? double speed master mode 23.2 overview the serial peripheral interface (spi) is a high-speed, full duplex, synchronous data transfer interface using three or four pins. it allows fast communication between an avr xmega device and peripheral devices or between several microcontrollers. a device connected to the bus must act as a master or slave. the master initiates and controls all data transactions. the interconnection between master and slave devices with spi is shown in figure 23-1 . the system consists of two shift registers and a clock generator. the spi master initiates t he communication by pulling the slave select (ss) signal low for the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interc hange data. data are always shifted from master to slave on the master output, slave input (mosi) line, and from slave to master on the master input, slave output (miso) line. after each data packet, the master can synchronize the slave by pulling the ss line high. figure 23-1. spi master -slave inte rconnection by default, the spi module is single buffered and transmit direction and double buffered in the receive direction. a byte written to the transmit data register will be copied to the shift register when a full character has been received. when receiving data, a received character must be read from the transmit data register before the third character has been completely shifted in to avoid losing data. optionally, buffer modes can be enabled. when used, one buffer is available for transmitter and a double buffer for reception. portc has one spi. notation of this is spic 8-bit shift register msb transmit data register (data) receive buffer register receive data register (data) mosi lsb miso sck ss slave 8-bit shift register msb transmit data register (data) receive buffer register receive data register (data) mosi lsb miso sck ss master spi clock generator
44 xmega e5 [datasheet] 8153f?avr?08/2013 24. usart 24.1 features ? two identical usart peripherals ? full-duplex or one-wire half-duplex operation ? asynchronous or synchronous operation ? synchronous clock rates up to 1/2 of the device clock frequency ? asynchronous clock rates up to 1/8 of the device clock frequency ? supports serial frames with: ? 5, 6, 7, 8, or 9 data bits ? optionally even and odd parity bits ? 1 or 2 stop bits ? fractional baud rate generator ? can generate desired baud rate from any system clock frequency ? no need for external oscillator with certain frequencies ? built-in error detection and correction schemes ? odd or even parity generation and parity check ? data overrun and framing error detection ? noise filtering includes false start bit detection and digital low-pass filter ? separate interrupts for ? transmit complete ? transmit data register empty ? receive complete ? multiprocessor communication mode ? addressing scheme to address a specif ic devices on a multidevice bus ? enable unaddressed devices to automatically ignore all frames ? system wake-up from start bit ? master spi mode ? double buffered operation ? configurable data order ? operation up to 1/2 of the peripheral clock frequency ? ircom module for irda compliant pulse modulation/demodulation ? one usart is connected to xmega custom logic (xcl) module: ? extend serial frame length up to 256 bit by using the peripheral counter ? modulate/demodulate data within the frame by using the glue logic outputs 24.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a fast and flexible serial communication module. the usart supports full-duplex with asynchronous and synchronous operation and single wire half-duplex communication with asynchronous operation. the usart can be configured to operate in spi master mode and used for spi communication. communication is frame based, and the frame format c an be customized to support a wide range of standards. the usart is buffered in both directions, enabling continued dat a transmission without any delay between frames. separate interrupts for receive and transmit complete enable fully interrupt driven communication. frame error and buffer overflow are detected in hardware and indicated with separate st atus flags. even or odd parity generation and parity check can also be enabled.
45 xmega e5 [datasheet] 8153f?avr?08/2013 in one-wire configuration, the txd pin is connected to the rxd pin internally, limiting the io pins usage. if the receiver is enabled when transmitting, it will receive what the transmitte r is sending. this mode can be used for bit error detection. the clock generator includes a fractional baud rate generator that is able to generate a wide range of usart baud rates from any system clock frequencies. this removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. it also supports exte rnal clock input in synchronous slave operation. an ircom module can be enabled for one usart to suppor t irda 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2kbps. one usart can be connected to the xmega custom logic module (xcl). when used with the xcl, the data length within an usart/spi frame can be controlled by the peripheral counter (pec) within the xcl. this enables configurable frame length up to 256 bits. in addition, the txd/rxd data can be encoded/decoded before the signal is fed into the usart receiver, or after the signal is output from transmitter when the usart is connected to xcl lut outputs. when the usart is set in master spi mode, all usart-spec ific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. the r egisters are used in both modes, but their functionality differs for some control settings. pin control and interrupt generation are identical in both modes. portc and portd each has one usart. notation of thes e peripherals are usartc0 and usartd0, respectively.
46 xmega e5 [datasheet] 8153f?avr?08/2013 25. ircom ? ir communication module 25.1 features ? pulse modulation/demodulation for infrared communication ? irda compatible for baud rates up to 115.2kbps ? selectable pulse modulation scheme ? 3/16 of the baud rate period ? fixed pulse period, 8-bit programmable ? pulse modulation disabled ? built-in filtering ? can be connected to and used by any usart 25.2 overview atmel avr xmega devices contain an infrared communication mo dule (ircom) that is irda compatible for baud rates up to 115.2kbps. it can be connected to any usart to enable infrared pulse encoding/decoding for that usart.
47 xmega e5 [datasheet] 8153f?avr?08/2013 26. xcl ? xmega custom logic module 26.1 features ? two independent 8-bit timer/counter with: ? period and compare channel for each timer/counter ? input capture for each timer ? serial peripheral data length control for each timer ? timeout support for each timer ? timer underflow interrupt/event ? compare match or input capture interrupt/event for each timer ? one 16-bit timer/counter by cascading two 8-bit timer/counters with: ? period and compare channel ? input capture ? timeout support ? timer underflow interrupt/event ? compare match or input capture interrupt/event ? programmable lookup table supporting multiple configurations: ? two 2-input units ? one 3-input unit ? rs configuration ? duplicate input with selectable delay on one input or output ? connection to external i/o pins, ev ent system or one selectable usart ? combinatorial logic functions using programmable truth table: ? and, nand, or, nor, xor, xnor, not, mux ? sequential logic functions: ? d-flip-flop, d latch, rs latch ? input sources: ? from external pins or the event system ? one input source includes select able delay or synchronizing option ? can be shared with selectable usart pin locations ? outputs: ? available on external pins or event system ? includes selectable delay or synchronizing option ? can override selectable usart pin locations ? operates in active mode and all sleep modes 26.2 overview the xmega custom logic module (xcl) consists of two sub- units, each including 8-bit timer/counter with flexible settings, peripheral counter working with one software sele ctable usart module, delay elements, glue logic with programmable truth table and a global logic interconnect array. the timer/counter configuration allows for two 8-bits timer/counters. each timer/counter supports normal, compare and input capture operation, with common flexible clock selections and event channels for each timer. by cascading the two 8-bit timer/counters, the xcl can be used as a 16-bit timer/counter. the peripheral counter (pec) configuration, the xcl is connected to one software selectable usart. this usart controls the counter operation, and the pec can optionally control the data length within the usart frame. the glue logic configuration, the xcl implements two program mable lookup tables (luts). each defines the truth table corresponding to the logical condition between two inputs. any co mbinatorial function logic is possible. the lut inputs can be connected to i/o pins or event system channels. if t he lut is connected to the usart0 pin locations, the data
48 xmega e5 [datasheet] 8153f?avr?08/2013 lines (txd/rxd) data encoding/decoding will be possible. connecting together the lut units, rs latch or any combinatorial logic between two oper ands or three inputs can be enabled. the lut works in all sleep modes. combined with event system and one i/o pin, the lut can wake-up the system if, and only if, condition on up to 3 input pins is true. a block diagram of the programmable logic unit with extensi ons and closely related peripheral modules (in grey) is shown in figure 26-1 . figure 26-1. xmega custom logic modu le and closely related peripherals. interrupts interconnect array interconnect array glue logic lut1 lut0 truth table truth table d q d q g timer/counter btc0 8-bit t/c normal capture pwm one shot periph.counter btc1 one shot pwm capture normal periph.counter 8-bit t/c control registers event system port pins usart
49 xmega e5 [datasheet] 8153f?avr?08/2013 27. crc ? cyclic redu ndancy check generator 27.1 features ? cyclic redundancy check (crc) generation and checking for ? communication data ? program or data in flash memory ? data in sram and i/o memory space ? integrated with flash memory, edma controller and cpu ? continuous crc on data going through an edma channel ? automatic crc of the complete or a selectable range of the flash memory ? cpu can load data to the crc generator through the i/o interface ? crc polynomial software selectable to ? crc-16 (crc-ccitt) ? crc-32 (ieee 802.3) ? zero remainder detection 27.2 overview a cyclic redundancy check (crc) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a dat a transmission, and data present in the data and program memories. a crc takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. when the same data are later received or read, the device or application repeats the calculation. if the new crc result does not match the one calculated earlier, the block contains a data error. the application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. typically, an n-bit crc applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2 -n of all longer error bursts. the crc module in xmega devices supports two commonly used crc polynomials; crc-16 (crc-ccitt) and crc-32 (ieee 802.3). ? crc-16: ? polynomial: x 16 + x 12 + x 5 + 1 ? hex value: 0x1021 ? crc-32: ? polynomial: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? hex value: 0x04c11db7
50 xmega e5 [datasheet] 8153f?avr?08/2013 28. adc ? 12-bit analog to digital converter 28.1 features ? 12-bit resolution ? up to 300 thousand samples per second ? down to 2.3 s conversion time with 8-bit resolution ? down to 3.35 s conversion time with 12-bit resolution ? differential and single-ended input ? up to 16 single-ended inputs ? 16x8 differential inputs with optional gain ? built-in differential gain stage ? 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options ? single, continuous and scan conversion options ? four internal inputs ? internal temperature sensor ? dac output ? v cc voltage divided by 10 ? 1.1v bandgap voltage ? internal and external reference options ? compare function for accurate monitoring of user defined thresholds ? offset and gain correction ? averaging ? over-sampling and decimation ? optional event triggered conversion for accurate timing ? optional interrupt/event on compare result ? optional edma transfer of conversion results 28.2 overview the adc converts analog signals to digital values. the adc has 12-bit resolution and is capable of converting up to 300 thousand samples per second (ksps). the input select ion is flexible, and both single-ended and differential measurements can be done. for differential measurements, an op tional gain stage is available to increase the dynamic range. in addition, several internal signal inputs are available. the adc can provide both signed and unsigned results. the adc measurements can either be started by applicati on software or an incoming event from another peripheral in the device. the adc measurements can be started with predi ctable timing, and without software intervention. it is possible to use edma to move adc results directly to memory or peripherals when conversions are done. both internal and external reference voltages can be used. an integrated temperature sensor is available for use with the adc. the output from the dac, vcc/10 and the bandgap voltage can also be measured by the adc. the adc has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. when operation in noisy conditions, the average feature can be enabled to increase the adc resolution. up to 1024 samples can be averaged, enabling up to 16-bit resolution resu lts. in the same way, using the over-sampling and decimation mode, the adc resolution is increased up to 16-bits, which results in up to 4-bit extra lsb resolution. the adc includes various calibration options. in addition to standard production calibration, the user can enable the offset and gain correction to improve the absolute adc accuracy.
51 xmega e5 [datasheet] 8153f?avr?08/2013 figure 28-1. adc overview. the adc may be configured for 8- or 12-bit result, reducing t he propagation delay from 3.35s for 12-bit to 2.3s for 8-bit result. adc conversion results are provided left- or right adjusted with eases calculation when the result is represented as a signed. porta has one adc. notation of this peripheral is adca. adc digital correction logic 2 2 clk adc v inp v inn stage 1 stage 2 ?x - 64x s&h adc dac 2x 2 bits v in v out reference voltage internal 1.00v internal vcc/1.6 arefa arefd internal vcc/2 internal signals adc1 a dc14 ? ? ? adc0 adc7 ? ? ? adc0 a dc15 threshold (int. req.) res cmp < > averaging gain & offset error correction
52 xmega e5 [datasheet] 8153f?avr?08/2013 29. dac ? digital to analog converter 29.1 features ? one digital to analog converter (dac) ? 12-bit resolution ? two independent, continuous-drive output channels ? up to 1 million samples per second conversion rate per dac channel ? built-in calibration that removes: ? offset error ? gain error ? multiple conversion trigger sources ? on new available data ? events from the event system ? drive capabilities and support for ? resistive loads ? capacitive loads ? combined resistive and capacitive loads ? internal and external reference options ? dac output available as input to analog comparator and adc ? low-power mode, with reduced drive strength ? optional edma transfer of data 29.2 overview the digital-to-analog converter (dac) converts digital val ues to voltages. the dac has two channels, each with 12-bit resolution, and is capable of converting up to one million samples per second (msps) on each channel. the built-in calibration system can remove offset and gain error when loaded with calibration values from software. figure 29-1. dac overview. a dac conversion is automatically started when new data to be converted are available. events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the dac and other peripherals, such as a timer/counter. the edma controller can be used to transfer data to the dac. dac0 dac1 ctrla ch1data ch0data trigger trigger internal output enable enable internal 1.00v arefa reference selection avcc output driver output driver d a t a int. driver d a t a ctrlb edma req (data empty) edma req (data empty) select 12 12 select enable to ac/adc arefd
53 xmega e5 [datasheet] 8153f?avr?08/2013 the dac is capable of driving both resistive and capacitive loads aswell as loads which combine both. a low-power mode is available, which will reduce the drive strength of the output. internal and external voltage references can be used. the dac output is also internally available for use as input to the analog comparator or adc. porta has one dac. notation of this peripheral is daca.
54 xmega e5 [datasheet] 8153f?avr?08/2013 30. ac ? analog comparator 30.1 features ? two analog comparators ? selectable propagation delay ? selectable hysteresis ? no ? small ? large ? analog comparator output available on pin ? flexible input selection ? all pins on the port ? output from the dac ? bandgap reference voltage. ? a 64-level programmable voltage scaler of the internal vcc voltage ? interrupt and event generation on ? rising edge ? falling edge ? toggle ? window function interrupt and event generation on ? signal above window ? signal inside window ? signal below window ? constant current source with configurable output pin selection ? source of asynchronous event 30.2 overview the analog comparator (ac) compares the voltage level on two inputs and gives a digital output based on this comparison. the analog comparator may be configured to give interrupt requests and/or synchronous/asynchronous events upon several different combinations of input change. one important property of the analog comparator when it comes to the dynamic behavior, is the hysteresis. this parameter may be adjusted in order to find the optimal operation for each application. the input section includes analog port pins, several inter nal signals and a 64-level programmable voltage scaler. the analog comparator output state can also be directly available on a pin for use by external devices. using as pair they can also be set in window mode to monitor a signal compared to a voltage window instead of a voltage level. a constant current source can be enabled and output on a selectable pin. this can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. the analog comparators are always grouped in pairs on eac h port. these are called analog comparator 0 (ac0) and analog comparator 1 (ac1). they have identical behavior, but separate control registers. used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. porta has one ac pair. notation is aca.
55 xmega e5 [datasheet] 8153f?avr?08/2013 figure 30-1. analog comparator overview. the window function is realized by connecting the external i nputs of the two analog comparators in a pair as shown in figure 30-2 . figure 30-2. analog comparator window function. voltage scaler acnmuxctrl acnctrl interrupt mode enable enable hysteresis hysteresis dac bandgap ac1out winctrl interrupt sensititivity control & window function events interrupts ac0out pin input pin input pin input pin input ac0 + - ac1 + - input signal upper limit of window lower limit of window interrupt sensitivity control interrupts events
56 xmega e5 [datasheet] 8153f?avr?08/2013 31. programming and debugging 31.1 features ? programming ? external programming through pdi interface ? minimal protocol overhead for fast operation ? built-in error detection and handling for reliable operation ? boot loader support for programming through any communication interface ? debugging ? nonintrusive, real-time, on-chip debug system ? no software or hardware resources required from device except pin connection ? program flow control ? go, stop, reset, step into, step over, step out, run-to-cursor ? unlimited number of user program breakpoints ? unlimited number of user data breakpoints, break on: ? data location read, write, or both read and write ? data location content equal or not equal to a value ? data location content is greater or smaller than a value ? data location content is within or outside a range ? no limitation on device clock frequency ? program and debug interface (pdi) ? two-pin interface for external programming and debugging ? uses the reset pin and a dedicated pin ? no i/o pins required during programming or debugging 31.2 overview the program and debug interface (pdi) is an atmel proprie tary interface for external programming and on-chip debugging of a device. the pdi supports fast programming of nonvolatile memory (nvm) spaces; flash, eepom, fuses, lock bits, and the user signature row. debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. it does not require any software or hardware resources except for the device pin connection. using the atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. application debug can be done from a c or other high-level language source code level, as well as from an assembler and disassemble level. programming and debugging can be done through the pdi physical layer. this is a two-pin interface that uses the reset pin for the clock input (pdi_clk) and one other dedicated pi n for data input and output (pdi_data). any external programmer or on-chip debugger/emulator can be directly connected to this interface.
57 xmega e5 [datasheet] 8153f?avr?08/2013 32. pinout and pin functions the device pinout is shown in pinout and block diagram on page 3. in addition to general purpose i/o functionality, each pin can have several alternate functions. this will depend on which peripheral is enabled and connected to the actual pin. only one of the pin functions can be used at time. 32.1 alternate pin f unction description the tables below show the notation for all pin functions available and describe its function. 32.1.1 operation/power supply 32.1.2 port interrupt functions 32.1.3 analog functions 32.1.4 timer/counter and wex functions 32.1.5 communication functions v cc digital supply voltage av cc analog supply voltage gnd ground sync port pin with full synchronous and limi ted asynchronous interrupt function async port pin with full synchronous and full asynchronous interrupt function acn analog comparator input pin n acnout analog comparator n output adcn analog to digital converter input pin n dacn digital to analog converter output pin n a ref analog reference input pin ocnx output compare channel x for timer/counter n ocnxls output compare channel x low side for timer/counter n ocnxhs output compare channel x high side for timer/counter n scl serial clock for twi sda serial data for twi sclin serial clock in for twi when external driver interface is enabled sclout serial clock out for twi when external driver interface is enabled
58 xmega e5 [datasheet] 8153f?avr?08/2013 32.1.6 oscillators, clock and event 32.1.7 debug/system functions sdain serial data in for twi when external driver interface is enabled sdaout serial data out for twi when external driver interface is enabled xckn transfer clock for usart n rxdn receiver data for usart n txdn transmitter data for usart n ss slave select for spi mosi master out slave in for spi miso master in slave out for spi sck serial clock for spi toscn timer oscillator pin n xtaln input/output for oscillator pin n clkout peripheral clock output evout event channel output rtcout rtc clock source output reset reset pin pdi_clk program and debug interface clock pin pdi_data program and debug interface data pin
59 xmega e5 [datasheet] 8153f?avr?08/2013 32.2 alternate pin functions the tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. the head row shows what peripheral that enable and use the alternate pin functions. for better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under th e first table where this apply. table 32-1. port a ? alternate functions. table 32-2. port c ? alternate functions. table 32-3. debug ? program and debug functions. port a pin# adca pos/ gainpos adca neg/ gainneg daca aca pos aca neg aca out refa pa0 6 adc 0 adc 0 ac0 ac0 aref pa1 5 adc 1 adc 1 ac1 ac1 pa2 4 adc 2 adc 2 dac0 ac2 pa3 3 adc 3 adc 3 dac1 ac3 ac3 pa4 2 adc 4 adc 4 ac4 pa5 31 adc 5 adc 5 ac5 ac5 pa6 30 adc 6 adc 6 ac6 ac1out pa7 29 adc 7 adc 7 ac7 ac0out port c pin # tcc4 wexc tcc5 usartc0 spic twi xcl (lut) extclk ac out pc0 16 oc4a oc4als sda in1/out0 pc1 15 oc4b oc4ahs xck0 scl in2 pc2 14 oc4c oc4bls rxd0 in0 pc3 13 oc4d oc4bhs txd0 in3 pc4 12 oc4a oc4cls oc5a ss in1/out0 extclk pc5 11 oc4b oc4chs oc5b xck0 sck in2 pc6 10 oc4c oc4dls rxd0 miso in0 ac1out pc7 9 oc4d oc4dhs txd0 mosi in3 ac0out debug pin # prog reset 8 pdi clock pdi 7 pdi data
60 xmega e5 [datasheet] 8153f?avr?08/2013 table 32-4. port r ? alternate functions. table 32-5. port d ? alternate functions. port r pin # xtal tosc extclk clockout eventout rtcout ac out pr0 20 xtal2 tosc2 clkout evout rtcout ac1 out pr1 19 xtal1 tosc1 extclk ac0 out port d pin # adcapos gainpos tcd5 usart d0 twid (bridge) xcl (lut) xcl (tc) clock out event out rtcout acout refd pd0 28 adc8 sda in1/ out0 aref pd1 27 adc9 xck0 scl in2 pd2 26 adc10 rxd0 in0 oc0 pd3 25 adc11 txd0 in3 oc1 pd4 24 adc12 oc5a in1/ out0 clkout evout pd5 23 adc13 oc5b xck0 in2 pd6 22 adc14 rxd0 in0 rtcout ac1out pd7 21 adc15 txd0 in3 clkout evout ac0out
61 xmega e5 [datasheet] 8153f?avr?08/2013 33. peripheral modu le address map the address maps show the base address for each peripher al and module in xmega e5. for complete register description and summary for each peripheral module, refer to the xmega e manual. table 33-1. peripheral module address map. base address name description 0x0000 gpio general purpose io registers 0x0010 vport0 virtual port a 0x0014 vport1 virtual port c 0x0018 vport2 virtual port d 0x001c vport3 virtual port r 0x0030 cpu cpu 0x0040 clk clock control 0x0048 sleep sleep controller 0x0050 osc oscillator control 0x0060 dfllrc32m dfll for the 32mhz internal oscillator 0x0070 pr power reduction 0x0078 rst reset controller 0x0080 wdt watch-dog timer 0x0090 mcu mcu control 0x00a0 pmic programmable multilevel interrupt controller 0x00b0 portcfg port configuration 0x00d0 crc crc module 0x0100 edma enhanced dma controller 0x0180 evsys event system 0x01c0 nvm non volatile memory (nvm) controller 0x0200 adca analog to digital converter on port a 0x0300 daca digital to analog converter on port a 0x0380 aca analog comparator pair on port a 0x0400 rtc real time counter 0x0460 xcl xmega custom logic module 0x0480 twic two-wire interface on port c 0x0600 porta port a 0x0640 portc port c
62 xmega e5 [datasheet] 8153f?avr?08/2013 0x0660 portd port d 0x07e0 portr port r 0x0800 tcc4 timer/counter 4 on port c 0x0840 tcc5 timer/counter 5 on port c 0x0880 faultc4 fault extension on tcc4 0x0890 faultc5 fault extensionon tcc5 0x08a0 wexc waveform extension on port c 0x08b0 hiresc high resolution extension on port c 0x08c0 usartc0 usart 0 on port c 0x08e0 spic serial peripheral interface on port c 0x08f8 ircom infrared communication module 0x0940 tcd5 timer/counter 5 on port d 0x09c0 usartd0 usart 0 on port d base address name description
63 xmega e5 [datasheet] 8153f?avr?08/2013 34. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd ? rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd ? rd + rr + c z,c,n,v,s,h 1 adiw rd, k add immediate to word rd ? rd + 1:rd + k z,c,n,v,s 2 sub rd, rr subtract without carry rd ? rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd ? rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd ? rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd ? rd - k - c z,c,n,v,s,h 1 sbiw rd, k subtract immediate from word rd + 1:rd ? rd + 1:rd - k z,c,n,v,s 2 and rd, rr logical and rd ? rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd ? rd ? k z,n,v,s 1 or rd, rr logical or rd ? rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd ? rd v k z,n,v,s 1 eor rd, rr exclusive or rd ? rd ? rr z,n,v,s 1 com rd one?s complement rd ? $ff - rd z,c,n,v,s 1 neg rd two?s complement rd ? $00 - rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd ? rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd ? rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd ? rd + 1 z,n,v,s 1 dec rd decrement rd ? rd - 1 z,n,v,s 1 tst rd test for zero or minus rd ? rd ? rd z,n,v,s 1 clr rd clear register rd ? rd ? rd z,n,v,s 1 ser rd set register rd ? $ff none 1 mul rd,rr multiply unsigned r1:r0 ? rd x rr (uu) z,c 2 muls rd,rr multiply signed r1:r0 ? rd x rr (ss) z,c 2 mulsu rd,rr multiply signed with unsigned r1:r0 ? rd x rr (su) z,c 2 fmul rd,rr fractional multiply unsigned r1:r0 ? rd x rr<<1 (uu) z,c 2 fmuls rd,rr fractional multiply signed r1:r0 ? rd x rr<<1 (ss) z,c 2 fmulsu rd,rr fractional multiply signed with unsigned r1:r0 ? rd x rr<<1 (su) z,c 2 des k data encryption if (h = 0) then r15:r0 else if (h = 1) then r15:r0 ? ? encrypt(r15:r0, k) decrypt(r15:r0, k) 1/2 branch instructions rjmp k relative jump pc ? pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) pc(21:16) ? ? z, 0 none 2 eijmp extended indirect jump to (z) pc(15:0) pc(21:16) ? ? z, eind none 2 jmp k jump pc ? k none 3 rcall k relative call subroutine pc ? pc + k + 1 none 2 / 3 (1)
64 xmega e5 [datasheet] 8153f?avr?08/2013 icall indirect call to (z) pc(15:0) pc(21:16) ? ? z, 0 none 2 / 3 (1) eicall extended indirect call to (z) pc(15:0) pc(21:16) ? ? z, eind none 3 (1) call k call subroutine pc ? k none 3 / 4 (1) ret subroutine return pc ? stack none 4 / 5 (1) reti interrupt return pc ? stack i 4 / 5 (1) cpse rd,rr compare, skip if equal if (rd = rr) pc ? pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd - rr z,c,n,v,s,h 1 cpc rd,rr compare with carry rd - rr - c z,c,n,v,s,h 1 cpi rd,k compare with immediate rd - k z,c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc ? pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register set if (rr(b) = 1) pc ? pc + 2 or 3 none 1 / 2 / 3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc ? pc + 2 or 3 none 2 / 3 / 4 sbis a, b skip if bit in i/o register set if (i/o(a,b) =1) pc ? pc + 2 or 3 none 2 / 3 / 4 brbs s, k branch if status flag set if (sreg(s) = 1) then pc ? pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc ? pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1 / 2 brlt k branch if less than, signed if (n ? v= 1) then pc ? pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc ? pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if (i = 1) then pc ? pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if (i = 0) then pc ? pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr copy register rd ? rr none 1 movw rd, rr copy register pair rd+1:rd ? rr+1:rr none 1 ldi rd, k load immediate rd ? k none 1 mnemonics operands description operation flags #clocks
65 xmega e5 [datasheet] 8153f?avr?08/2013 lds rd, k load direct from data space rd ? (k) none 2 (1)(2) ld rd, x load indirect rd ? (x) none 1 (1)(2) ld rd, x+ load indirect and post-increment rd x ? ? (x) x + 1 none 1 (1)(2) ld rd, -x load indirect and pre-decrement x ? x - 1, rd ? (x) ? ? x - 1 (x) none 2 (1)(2) ld rd, y load indirect rd ? (y) ? (y) none 1 (1)(2) ld rd, y+ load indirect and post-increment rd y ? ? (y) y + 1 none 1 (1)(2) ld rd, -y load indirect and pre-decrement y rd ? ? y - 1 (y) none 2 (1)(2) ldd rd, y+q load indirect with displacement rd ? (y + q) none 2 (1)(2) ld rd, z load indirect rd ? (z) none 1 (1)(2) ld rd, z+ load indirect and post-increment rd z ? ? (z), z+1 none 1 (1)(2) ld rd, -z load indirect and pre-decrement z rd ? ? z - 1, (z) none 2 (1)(2) ldd rd, z+q load indirect with displacement rd ? (z + q) none 2 (1)(2) sts k, rr store direct to data space (k) ? rd none 2 (1) st x, rr store indirect (x) ? rr none 1 (1) st x+, rr store indirect and post-increment (x) x ? ? rr, x + 1 none 1 (1) st -x, rr store indirect and pre-decrement x (x) ? ? x - 1, rr none 2 (1) st y, r r store indirect (y) ? rr none 1 (1) st y+, rr store indirect and post-increment (y) y ? ? rr, y + 1 none 1 (1) st -y, rr store indirect and pre-decrement y (y) ? ? y - 1, rr none 2 (1) std y+q, rr store indirect with displacement (y + q) ? rr none 2 (1) st z, rr store indirect (z) ? rr none 1 (1) st z+, rr store indirect and post-increment (z) z ? ? rr z + 1 none 1 (1) st -z, rr store indirect and pre-decrement z ? z - 1 none 2 (1) std z+q,rr store indirect with displacement (z + q) ? rr none 2 (1) lpm load program memory r0 ? (z) none 3 lpm rd, z load program memory rd ? (z) none 3 lpm rd, z+ load program memory and post-increment rd z ? ? (z), z + 1 none 3 elpm extended load program memory r0 ? (rampz:z) none 3 elpm rd, z extended load program memory rd ? (rampz:z) none 3 elpm rd, z+ extended load program memory and post- increment rd z ? ? (rampz:z), z + 1 none 3 spm store program memory (rampz:z) ? r1:r0 none - spm z+ store program memory and post-increment by 2 (rampz:z) z ? ? r1:r0, z + 2 none - mnemonics operands description operation flags #clocks
66 xmega e5 [datasheet] 8153f?avr?08/2013 in rd, a in from i/o location rd ? i/o(a) none 1 out a, rr out to i/o location i/o(a) ? rr none 1 push rr push register on stack stack ? rr none 1 (1) pop rd pop register from stack rd ? stack none 2 (1) xch z, rd exchange ram location te m p rd (z) ? ? ? rd, (z), te m p none 2 las z, rd load and set ram location te m p rd (z) ? ? ? rd, (z), te m p v ( z ) none 2 lac z, rd load and clear ram location te m p rd (z) ? ? ? rd, (z), ($ffh ? rd) ? (z) none 2 lat z, rd load and toggle ram location te m p rd (z) ? ? ? rd, (z), te m p ? (z) none 2 bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(0) c ? ? ? rd(n), 0, rd(7) z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(7) c ? ? ? rd(n+1), 0, rd(0) z,c,n,v 1 rol rd rotate left through carry rd(0) rd(n+1) c ? ? ? c, rd(n), rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) rd(n) c ? ? ? c, rd(n+1), rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 sbi a, b set bit in i/o register i/o(a, b) ? 1 none 1 cbi a, b clear bit in i/o register i/o(a, b) ? 0 none 1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? t none 1 sec set carry c ? 1 c 1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1 n 1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1 z 1 clz clear zero flag z ? 0 z 1 sei global interrupt enable i ? 1 i 1 cli global interrupt disable i ? 0 i 1 ses set signed test flag s ? 1 s 1 cls clear signed test flag s ? 0 s 1 mnemonics operands description operation flags #clocks
67 xmega e5 [datasheet] 8153f?avr?08/2013 notes: 1. cycle times for data memo ry accesses assume internal memory accesses, and are not valid for accesses via the external r am interface. 2. one extra cycle must be added when accessing internal sram. sev set two?s complement overflow v ? 1 v 1 clv clear two?s complement overflow v ? 0 v 1 set set t in sreg t ? 1 t 1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1 h 1 clh clear half carry flag in sreg h ? 0 h 1 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 wdr watchdog reset (see specific descr. for wdr) none 1 mnemonics operands description operation flags #clocks
68 xmega e5 [datasheet] 8153f?avr?08/2013 35. packaging information 35.1 32a
69 xmega e5 [datasheet] 8153f?avr?08/2013 35.2 32z
70 xmega e5 [datasheet] 8153f?avr?08/2013 35.3 32ma
71 xmega e5 [datasheet] 8153f?avr?08/2013 36. electrical characteristics all typical values are measured at t = 25 c unless other temperature condition is given. all minimum and maximum values are valid across operating temperatur e and voltage unless other conditions are given. 36.1 absolute maximum ratings 36.2 general operating ratings the device must operate within the ratings listed in table 36-1 in order for all other electr ical characteristics and typical characteristics of the device to be valid. table 36-1. general operating conditions. table 36-2. operating voltage and frequency. the maximum cpu clock frequency depends on v cc . as shown in figure 36-1 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. symbol parameter min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 ma v pin pin voltage with respect to gnd and v cc -0.5 v cc +0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 c symbol parameter min. typ. max. units v cc power supply voltage 1.6 3.6 v av cc analog supply voltage 1.6 3.6 v t a temperature range -40 85 c t j junction temperature -40 105 c symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
72 xmega e5 [datasheet] 8153f?avr?08/2013 figure 36-1. maximum frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
73 xmega e5 [datasheet] 8153f?avr?08/2013 36.3 current consumption table 36-3. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 20 a v cc = 3.0v 30 1mhz, ext. clk v cc = 1.8v 140 v cc = 3.0v 270 2mhz, ext. clk v cc = 1.8v 280 400 v cc = 3.0v 0.6 1.2 ma 32mhz, ext. clk v cc = 3.0v 6 10 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 5 a v cc = 3.0v 10 1mhz, ext. clk v cc = 1.8v 55 v cc = 3.0v 100 2mhz, ext. clk v cc = 1.8v 110 250 v cc = 3.0v 200 350 32mhz, ext. clk v cc = 3.0v 3.5 5 ma power-down power consumption all disabled, t = 25c v cc = 3.0v 0.1 0.9 a all disabled, t = 85c 1 3 wdt and sampled bod enabled, t=25c v cc = 3.0v 0.5 wdt and sampled bod enabled, t = 85c 1.2 3.5 power-save power consumption rtc from ulp clock, wdt and sampled bod enabled, t = 25 ? c v cc = 1.8v 0.4 a v cc = 3.0v 0.6 rtc from ulp clock, wdt, sampled bod enabled and 8mhz internal oscillator in low power mode, t = 25 ? c v cc = 1.8v 0.5 v cc = 3.0v 0.6 rtc on 1khz low power 32.768khz tosc, t = 25 ? c v cc = 1.8v 0.8 v cc = 3.0v 0.9 rtc from low power 32.768khz tosc, t = 25 ? c v cc = 1.8v 0.9 v cc = 3.0v 1.0 reset power consumption current through reset pin substracted, t = 25c v cc = 3.0v 110 a
74 xmega e5 [datasheet] 8153f?avr?08/2013 table 36-4. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current cons umption between module enabled and disabled. all data at vcc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc internal ulp oscillator 100 na 32.768khz int. oscillator 27 a 8mhz int. oscillator normal power mode 65 a low power mode 45 32mhz int. oscillator 275 a dfll enabled with 32.768khz int. osc. as reference 400 pll 20x multiplication factor, 32mhz int. osc. div4 as reference 230 a watchdog timer 0.3 a bod continuous mode 245 a sampled mode 0.4 internal 1.0v reference 200 a internal temperature sensor 100 a adc 16ksps v ref = ext ref 1.5 ma currlimit = low 1.4 currlimit = medium 1.3 currlimit = high 1.2 75ksps, v ref = ext ref currlimit = low 1.7 300ksps, v ref = ext ref 3.1 dac 250ksps v ref = ext ref no load normal mode 1.9 ma low power mode 1.1 ac 200 a edma 200 a timer/counter 25 a usart rx and tx enabled, 9600 baud 8 a xcl 16-bit timer/counter 6 a flash memory and eeprom programming 4 ma
75 xmega e5 [datasheet] 8153f?avr?08/2013 36.4 wake-up time from sleep modes table 36-5. device wake-up time from sleep mo des with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 36-2 . all peripherals and modules start execution from the first clock cycle, expect the cp u that is halted for four clock cycles before program executio n starts. figure 36-2. wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 0.2 s 32khz internal oscillator 120 8mhz internal oscillator 0.5 32mhz internal oscillator 0.2 wake-up time from power save mode external 2mhz clock 4.5 32khz internal oscillator 320 8mhz internal oscillator normal mode 4.5 low power mode 0.5 32mhz internal oscillator 0.2 wake-up time from power down mode external 2mhz clock 4.5 32khz internal oscillator 320 8mhz internal oscillator 4.5 32mhz internal oscillator 5.0 wakeup request clock output wakeup time
76 xmega e5 [datasheet] 8153f?avr?08/2013 36.5 i/o pin ch aracteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 36-6. i/o pin characteristics. notes: 1. the sum of all i oh for pa[7:5] on porta must not exceed 100ma. the sum of all i oh for pa[4:0] on porta must not exceed 200ma. the sum of all i oh for portd and portr must not exceed 100ma. the sum of all i oh for portc and pdi must not exceed 100ma. 2. the sum of all i ol for pa[7:5] on porta must not exceed 100ma. the sum of all i ol for pa[4:0] on porta must not exceed 100ma. the sum of all i ol for portd and portr must not exceed 100ma. the sum of all i ol for portc pdi must not exceed 100ma. 36.6 adc characteristics table 36-7. power supply, reference and input range. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -15 15 ma v ih high level input voltage, except xtal1 and reset pin v cc = 2.4 - 3.6v 0.7*v cc v cc +0.5 v v cc = 1.6 - 2.4v 0.8*v cc v cc +0.5 v il low level input voltage, except xtal1 and reset pin v cc = 2.4- 3.6v -0.5 0.3*v cc v v cc = 1.6 - 2.4v -0.5 0.2*v cc v oh high level output voltage v cc = 3.3v i oh = -4ma 2.6 3.1 v v cc = 3.0v i oh = -3ma 2.1 2.7 v cc = 1.8v i oh = -1ma 1.4 1.7 v ol low level output voltage v cc = 3.3v i ol = 8ma 0.20 0.76 v v cc = 3.0v i ol = 5ma 0.15 0.64 v cc = 1.8v i ol = 3ma 0.10 0.46 i in input leakage current t = 25c <0.01 1.0 a r p pull/buss keeper resistor 27 k ? symbol parameter condition min. typ. max. units avcc analog supply voltage v cc - 0.3 v cc + 0.3 v vref reference voltage 1 av cc - 0.6 v r in input resistance switched 4.5 k ? c in input capacitance switched 5 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf
77 xmega e5 [datasheet] 8153f?avr?08/2013 table 36-8. clock and timing. table 36-9. accuracy characteristics. vin input range 0 v ref v vin conversion range differential mode, vinp - vinn -0.95*v ref 0.95*v ref v vin conversion range single ended unsigned mode, vinp -0.05*v ref 0.95*v ref v symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 1800 khz measuring internal signals 125 f clkadc sample rate 16 300 ksps f adc sample rate current limitation (currlimit) off 16 300 ksps currlimit = low 250 currlimit = medium 150 currlimit = high 50 sampling time 1/2 clk adc cycle 0.25 5 s conversion time (latency) (res+2)/2+(gain !=0) res (resolution) = 8 or 12 6 10 clk adc cycles start-up time adc clock cycles 12 24 clk adc cycles adc settling time after changing reference or input mode 7 7 clk adc cycles symbol parameter condition min. typ. max. units symbol parameter condition (2) min. typ. max. units res resolution 12-bit resolution differential 8 12 12 bits single ended signed 7 11 11 single ended unsigned 8 12 12 inl (1) integral non-linearity differential mode 16ksps, vref = 3v 1 lsb 16ksps, vref = 1v 2 300ksps, vref = 3v 1 300ksps, vref = 1v 2 single ended unsigned mode 16ksps, vref = 3.0v 1 1.5 16ksps, vref = 1.0v 2 3
78 xmega e5 [datasheet] 8153f?avr?08/2013 notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 10% to 90% input voltage rang e. 2. unless otherwise noted all linearity, offset and gain error numbe rs are valid under the condition that external vref is used. table 36-10. gain stage characteristics. dnl (1) differential non-linearity differential mode 16ksps, vref = 3v 1 lsb 16ksps, vref = 1v 2 300ksps, vref = 3v 1 300ksps, vref = 1v 2 single ended unsigned mode 16ksps, vref = 3.0v 1 1.5 16ksps, vref = 1.0v 2 3 offset error differential mode 8 mv temperature drift 0.01 mv/k operating voltage drift 0.25 mv/v gain error differential mode external reference -5 mv avcc/1.6 -5 avcc/2.0 -6 bandgap 10 temperature drift 0.02 mv/k operating voltage drift 2 mv/v gain error single ended unsigned mode external reference -8 mv avcc/1.6 -8 avcc/2.0 -8 bandgap 10 temperature drift 0.03 mv/k operating voltage drift 2 mv/v symbol parameter condition (2) min. typ. max. units symbol parameter condition min. typ. max. units r in input resistance switched 4.0 k ? c sample input capacitance switched 4.4 pf signal range gain stage output 0 av cc - 0.6 v propagation delay adc conversion rate 1/2 1 3 clk adc cycles clock rate same as adc 100 1800 khz
79 xmega e5 [datasheet] 8153f?avr?08/2013 36.7 dac characteristics table 36-11. power supply, reference and output range. table 36-12. clock and timing. gain error 0.5x gain -1 % 1x gain -1 8x gain -1 64x gain -1.5 offset error, input referred 0.5x gain 10 mv 1x gain 5 8x gain 5 64x gain 5 symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 av ref external reference voltage 1.0 v cc - 0.6 v r channel dc output impedance 50 ? linear output voltage range 0.15 vref-0.15 v r aref reference input resistance >10 m ? caref reference input capacitance static load 7 pf minimum resistance load 1 k ? maximum capacitance load 100 pf 1000 ? serial resistance 1 nf output sink/source operating within accuracy specification av cc /1000 ma safe operation 10 symbol parameter condition min. typ. max. units symbol parameter condition min. typ. max. units f dac conversion rate c load =100pf, maximum step size normal mode 0 1000 ksps low power mode 0 500
80 xmega e5 [datasheet] 8153f?avr?08/2013 table 36-13. accuracy characteristics. note: 1. maximum numbers are based on charac terisation and not tested in production, and valid for 5% to 95% output voltage range . symbol parameter condition min. typ. max. units res input resolution 12 bits inl (1) integral non-linearity v ref = ext 1.0v v cc = 1.6v 2.0 3 lsb v cc = 3.6v 1.5 2.5 v ref =av cc v cc = 1.6v 2.0 4 v cc = 3.6v 1.5 4 v ref =int1v v cc = 1.6v 5.0 v cc = 3.6v 5.0 dnl (1) differential non-linearity v ref =ext 1.0v v cc = 1.6v 1.5 3 lsb v cc = 3.6v 0.6 1.5 v ref =av cc v cc = 1.6v 1.0 3.5 v cc = 3.6v 0.6 1.5 v ref =int1v v cc = 1.6v 4.5 v cc = 3.6v 4.5 gain error after calibration <4 lsb gain calibration step size 4 lsb gain calibration drift v ref = ext 1.0v <0.2 mv/k offset error after calibration <1 lsb offset calibration step size 1
81 xmega e5 [datasheet] 8153f?avr?08/2013 36.8 analog comparat or characteristics table 36-14. analog comparator characteristics. 36.9 bandgap and internal 1.0v reference characteristics table 36-15. bandgap and internal 1.0v reference characteristics. symbol parameter condition min. typ. max. units v off input offset voltage 10 mv i lk input leakage current <10 50 na input voltage range -0.1 av cc v ac startup time 50 s v hys1 hysteresis, none v cc = 1.6v - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6v - 3.6v 12 mv v hys3 hysteresis, large v cc = 1.6v - 3.6v 28 mv t delay propagation delay v cc = 3.0v, t= 85c 22 30 ns v cc = 1.6v - 3.6v 21 40 64-level voltage scaler integral non- linearity (inl) 0.3 0.5 lsb current source accuracy after calibration 5 % current source calibration range single mode 4 6 a current source calibration range double mode 8 12 a symbol parameter condition min. typ. max. units startup time as reference for adc 1 clk per + 2.5 s s as input voltage to adc and ac 1.5 bandgap bandgap voltage 1.1 v int1v internal 1.00v reference for adc and dac t= 25c, after calibration 0.99 1.0 1.01 v variation over voltage and temperature calibrated at t= 25c 3 %
82 xmega e5 [datasheet] 8153f?avr?08/2013 36.9.1 brownout detection characteristics 36.10 external rese t characteristics table 36-16. external reset characteristics 36.11 power-on rese t characteristics table 36-17. power-on re set characteristics. note: 1. vpot- values are only valid when bod is disabled. when bod is enabled vpot- = vpot+. symbol parameter condition min. typ. max. units v bot bod level 0 falling v cc 1.50 1.65 1.75 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1.0 ms v hyst hysteresis bod level 0 - 7. min value measured at bod level 0 1.0 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 90 1000 ns v rst reset threshold voltage (v ih ) v cc = 2.7 - 3.6v 0.6*v cc v v cc = 1.6 - 2.7v 0.6*v cc reset threshold voltage (v il ) v cc = 2.7 - 3.6v 0.5*v cc v cc = 1.6 - 2.7v 0.4*v cc r rst reset pin pull-up resistor 25 k ? symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1 v/ms or slower 0.8 1.3 v pot+ por threshold voltage raising v cc 1.3 1.59 v
83 xmega e5 [datasheet] 8153f?avr?08/2013 36.12 flash and eeprom characteristics table 36-18. endurance and data retention. table 36-19. programming time. notes: 1. programming is timed from the 2m hz output of 8mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. parameter condition min. typ. max. units flash write/erase cycles 25 ? c 10k cycle 85c 10k data retention 25c 100 year 85c 25 eeprom write/erase cycles 25c 100k cycle 85c 100k data retention 25c 100 year 85c 25 parameter condition min. typ. (1) max. units chip erase 32kb flash, eeprom (2) 50 ms 16kb flash, eeprom (2) 45 8kb flash, eeprom (2) 42 flash page erase 4 ms page write 4 atomic page erase and write 8 eeprom page erase 4 ms page write 4 atomic page erase and write 8
84 xmega e5 [datasheet] 8153f?avr?08/2013 36.13 clock and oscillat or characteristics 36.13.1 calibrated 32.768khz internal oscillator characteristics table 36-20. 32.768khz internal oscillator characteristics. 36.13.2 calibrated 8mhz internal oscillator characteristics table 36-21. 8mhz internal o scillator characteristics. 36.13.3 calibrated and tunable 32mhz internal oscillator characteristics table 36-22. 32mhz internal oscillator characteristics . 36.13.4 32.768khz internal ulp oscillator characteristics table 36-23. 32.768khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 25c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 % symbol parameter condition min. typ. max. units frequency range 4.4 9.4 mhz factory calibrated frequency 8 mhz factory calibration accuracy t = 25c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 % symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 55 mhz factory calibrated frequency 32 mhz factory calibration accuracy t = 25c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration step size 0.23 % symbol parameter condition min. typ. max. units output frequency 32 khz accuracy -30 30 %
85 xmega e5 [datasheet] 8153f?avr?08/2013 36.13.5 internal phase locked loop (pll) characteristics table 36-24. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 36.13.6 external clock characteristics figure 36-3. external clock drive waveform. table 36-25. external clock used as system clock without prescaling. symbol parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 mhz v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 s t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
86 xmega e5 [datasheet] 8153f?avr?08/2013 note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. table 36-26. external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 36.13.7 external 16mhz crystal osci llator and xosc characteristics table 36-27. external 16mhz crystal oscillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 <10 ns frqrange=1, 2, or 3 <1 xoscpwr=1 <1 long term jitter xoscpwr=0 frqrange=0 <6 ns frqrange=1, 2, or 3 <0.5 xoscpwr=1 <0.5 frequency error xoscpwr=0 frqrange=0 <0.1 % frqrange=1 <0.05 frqrange=2 or 3 <0.005 xoscpwr=1 <0.005
87 xmega e5 [datasheet] 8153f?avr?08/2013 note: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization. duty cycle xoscpwr=0 frqrange=0 40 % frqrange=1 42 frqrange=2 or 3 45 xoscpwr=1 48 r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf ? 1mhz crystal, cl=20pf 2mhz crystal, cl=20pf xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 8mhz crystal 9mhz crystal xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 9mhz crystal 12mhz crystal xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 12mhz crystal 16mhz crystal xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 12mhz crystal 16mhz crystal xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 12mhz crystal 16mhz crystal xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 16mhz crystal xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 16mhz crystal c xtal1 parasitic capacitance xtal1 pin 5.4 pf c xtal2 parasitic capacitance xtal2 pin 7.1 c load parasitic capacitance load 3.07 symbol parameter condition min. typ. max. units
88 xmega e5 [datasheet] 8153f?avr?08/2013 36.13.8 external 32.768khz crystal os cillator and tosc characteristics table 36-28. external 32.768khz crystal o scillator and tosc characteristics. note: 1. see figure 36-4 for definition. figure 36-4. tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 c tosc1 parasitic capacitance tosc1 pin 5.3 pf c tosc2 parasitic capacitance tosc2 pin 7.4 pf recommended safety factor capacitance load matched to crystal specification 3.0 c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
89 xmega e5 [datasheet] 8153f?avr?08/2013 36.14 spi characteristics figure 36-5. spi timing requirements in master mode. figure 36-6. spi timing requirements in slave mode. msb lsb b s l b s m t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb b s l b s m t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
90 xmega e5 [datasheet] 8153f?avr?08/2013 table 36-29. spi timing characteristics and requirements. symbol parameter condition min. typ. max. units t sck sck period master ns t sckw sck high/low width master 0.5sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5sck t moh mosi hold after sck master 1.0 t ssck slave sck period slave 4t clk per t ssckw sck high/low width slave 2t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3.0 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8.0 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8.0
91 xmega e5 [datasheet] 8153f?avr?08/2013 36.15 two-wire interface characteristics table 36-6 on page 76 describes the requirements for devices connected to the two-wire interface (twi) bus. the atmel avr xmega twi meets or exceeds these requirement s under the noted conditions. timing symbols refer to figure 36- 7 . figure 36-7. two-wire interface bus timing table 36-30. two-wire interface characteristics. t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc +0.5 v v il input low voltage -0.5 0.3v cc v v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v v ol output low voltage 3ma, sink current 0 0.4 v i ol low level output current f scl 400khz v ol = 0.4v 3 ma f scl 1mhz 20 t r rise time for both sda and scl f scl 400khz 20+0.1c b (1)(2) 300 ns f scl 1mhz 120 t of output fall time from v ihmin to v ilmax 10pf< c b <400pf (2) f scl 400khz 20+0.1c b (1)(2) 250 ns f scl 1mhz 120 t sp spikes suppressed by input filter 0 50 ns i i input current for each i/o pin 0.1 v cc max(10f scl ,250khz) 0 1 mhz r p value of pull-up resistor f scl 100khz (v cc -0.4v) /i ol 100ns/c b ? f scl 400khz 300ns/c b f scl 1mhz 550ns/c b t hd;sta hold time (repeated) start condition f scl 100khz 4 s f scl 400khz 0.6 f scl 1mhz 0.26
92 xmega e5 [datasheet] 8153f?avr?08/2013 notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. t low low period of scl clock f scl 100khz 4.7 s f scl 400khz 1.3 f scl 1mhz 0.5 t high high period of scl clock f scl 100khz 4 s f scl 400khz 0.6 f scl 1mhz 0.26 t su;sta set-up time for a repeated start condition f scl 100khz 4.7 s f scl 400khz 0.6 f scl 1mhz 0.26 t hd;dat data hold time f scl 100khz 0 3.45 s f scl 400khz 0 0.9 f scl 1mhz 0 0.45 t su;dat data setup time f scl 100khz 250 ns f scl 400khz 100 f scl 1mhz 50 t su;sto setup time for stop condition f scl 100khz 4 s f scl 400khz 0.6 f scl 1mhz 0.26 t buf bus free time between a stop and start condition f scl 100khz 4.7 s f scl 400khz 1.3 f scl 1mhz 0.5 symbol parameter condition min. typ. max. units
93 xmega e5 [datasheet] 8153f?avr?08/2013 37. typical characteristics 37.1 current consumption 37.1.1 active mode supply current figure 37-1. active mode supply current vs. frequency. f sys = 0 ? 1mhz external clock, t = 25c figure 37-2. active mode supply current vs. frequency. f sys = 0 ? 32mhz external clock, t = 25c icc [ma] 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.0 0.2 0.4 0.6 0.8 1.0 frequency [mhz] v_cc_ 1.6 1.8 2.2 2.7 3 3.6 icc [ma] 0 1 2 3 4 5 6 7 8 9 0 4 8 12 16 20 24 28 32 frequency [mhz] v_cc_ 1.6 1.8 2.2 2.7 3 3.6
94 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-3. active mode supply current vs. v cc . f sys = 32.768khz internal oscillator figure 37-4. active mode supply current vs. v cc . f sys = 1mhz external clock icc [ua] 27.0 28.0 29.0 30.0 31.0 32.0 33.0 34.0 35.0 36.0 37.0 38.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 icc [ma] 0.10 0.15 0.20 0.25 0.30 0.35 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105
95 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-5. active mode supply current vs. v cc . f sys = 8mhz internal oscill ator prescaled to 2mhz figure 37-6. active mode supply current vs. v cc . f sys = 8mhz internal oscillator icc [ma] 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 icc [ma] 0.5 1.0 1.5 2.0 2.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105
96 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-7. active mode supply current vs. v cc . f sys = 32mhz internal oscill ator prescaled to 8mhz figure 37-8. active mode supply current vs. v cc . f sys = 32mhz internal oscillator icc [ma] 1.0 1.5 2.0 2.5 3.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 icc [ma] 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 vcc [v] tem perature -40 25 85 105
97 xmega e5 [datasheet] 8153f?avr?08/2013 37.1.2 idle mode supply current figure 37-9. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25 ? c . figure 37-10.idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25 ? c . icc [ua] 0 25 50 75 100 125 150 0.0 0.2 0.4 0.6 0.8 1.0 frequency [mhz] v_cc_ 1.600 1.800 2.200 2.700 3.000 3.600 y, icc [ma] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4 8 12 16 20 24 28 32 frequency [mhz] v_cc_ 1.6 1.8 2.2 2.7 3 3.6
98 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-11.idle mode supply current vs. v cc . f sys = 32.768khz internal oscillator figure 37-12.idle mode supply current vs. v cc . f sys = 1mhz external clock icc [ua] 25 26 27 28 29 30 31 32 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 icc [ua] 45.0 46.5 48.0 49.5 51.0 52.5 54.0 55.5 1.6 1.8 1.700 2.2 2.4 2.6 2.8 1.800 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105
99 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-13.idle mode supply current vs. v cc . f sys = 8mhz internal oscill ator prescaled to 2mhz figure 37-14.idle mode supply current vs. v cc . f sys = 8mhz internal oscillator. icc [ma] 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 icc [ma] 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105
100 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-15.idle mode supply current vs. v cc . f sys = 32mhz internal oscill ator prescaled to 8mhz . figure 37-16.idle mode supply current vs. v cc . f sys = 32mhz internal oscillator . icc [ma] 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 icc [ma] 2.5 3.0 3.5 4.0 4.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 vcc [v] tem perature -40 25 85 105
101 xmega e5 [datasheet] 8153f?avr?08/2013 37.1.3 power-down mode supply current figure 37-17.power-down mode supply current vs. temperature. all functions disabled . figure 37-18.power-down mode supply current vs. v cc . all functions disabled . icc [ua] 0.00 0.30 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00 -30 -15 0 15 30 45 60 75 90 105 temperature [c] v_cc_ 1.6 1.8 2.2 2.7 3 3.6 icc [ua] 0.00 0.30 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105
102 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-19.power-down mode supply current vs. temperature. sampled bod with watchdog timer running on ulp oscillator . 37.1.4 power-save m ode supply current figure 37-20.power-save mode supply current vs. v cc . real time counter enabled and running from 1.024khz output of 32.768khz tosc . idd [a] 0.725 0.730 0.735 0.740 0.745 0.750 0.755 0.760 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] idd [a] 0.800 0.850 0.900 0.950 1.000 1.050 1.100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v]
103 xmega e5 [datasheet] 8153f?avr?08/2013 37.1.5 standby mode supply current figure 37-21.standby supply current vs. v cc . standby, f sys =1mhz . figure 37-22.standby supply current vs. v cc . 25c, running from different crystal oscillators . icc [ua] 1 2 3 4 5 6 7 8 9 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 vcc [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 idd [a] 150 200 250 300 350 400 450 500 crystals 0.455mhz 12.0mhz 16.0mhz 2.0mhz 8.0mhz
104 xmega e5 [datasheet] 8153f?avr?08/2013 37.2 i/o pin ch aracteristics 37.2.1 pull-up figure 37-23.i/o pin pull-up resi stor current vs. input voltage. v cc = 1.8v . figure 37-24.i/o pin pull-up resi stor current vs. input voltage. v cc = 3.0v . ipin [ua] -70 -60 -50 -40 -30 -20 -10 0 10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 vpin [v] tem perature -40 25 85 105 ipin [ua] -120 -100 -80 -60 -40 -20 0 20 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 vpin [v] tem perature -40 25 85 105
105 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-25.i/o pin pull-up resi stor current vs. input voltage. v cc = 3.3v . 37.2.2 output voltage vs. sink/source current figure 37-26.i/o pin output voltage vs. source current. v cc = 1.8v . ipin [ua] -150 -100 -50 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 vpin [v] tem perature -40 25 85 105 vpin [v] 1.55 1.60 1.65 1.70 1.75 1.80 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 ipin [ma] temperature 25 85 105 -40
106 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-27.i/o pin output voltage vs. source current. v cc = 3.0v . figure 37-28.i/o pin output voltage vs. source current. v cc = 3.3v . vpin [v] 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 ipin [ma] temperature 25 85 105 -40 vpin [v] 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 ipin [ma] temperature 25 85 105 -40
107 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-29.i/o pin output voltage vs. source current. figure 37-30.i/o pin output voltage vs. sink current. v cc = 1.8v . , vpin [v] 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -18 -15 -12 -9 -6 -3 0 ipin [ma] v_cc_ 1.6 1.8 2.7 3 3.3 3.6 vpin [v] 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ipin [ma] temperature 25 85 105 -40
108 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-31.i/o pin output voltage vs. sink current. v cc = 3.0v . figure 37-32.i/o pin output voltage vs. sink current. v cc = 3.3v . vpin [v] 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 2 4 6 8 10 12 14 16 18 20 ipin [ma] temperature 25 85 105 -40 vpin [v] 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 2 4 6 8 10 12 14 16 18 20 ipin [ma] temperature 25 85 105 -40
109 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-33.i/o pin output voltage vs. sink current. 37.2.3 thresholds and hysteresis figure 37-34.i/o pin input threshold voltage vs. v cc. t = 25c . vpin [v] 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 0 2 4 6 8 10 12 14 16 18 20 ipin [ma] v_cc_ 1.6 1.8 2.7 3 3.3 3.6 vthreshold [v] 0.75 0.90 1.05 1.20 1.35 1.50 1.65 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] test info vih vil
110 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-35.i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? figure 37-36.i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? vthreshold [v] 0.60 0.80 1.00 1.20 1.40 1.60 1.80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 vthreshold [v] 0.60 0.80 1.00 1.20 1.40 1.60 1.80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105
111 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-37.i/o pin input hysteresis vs. v cc . 37.3 adc characteristics figure 37-38.adc inl vs. v ref . t = 25 ? c, v cc = 3.6v, external reference . vhysteresis [v] 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 inl [lsb] 0.25 0.50 0.75 1.00 1.25 1.50 1.75 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 vref [v] mode differential mode single-ended signed mode single-ended unsigned mode
112 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-39.adc inl error vs. v cc . t = 25 ? c, v ref = 1.0v figure 37-40.adc dnl error vs. v ref . se unsigned mode, t=25 ? c, v cc = 3.6v, external reference . inl [lsb] 0.60 0.80 1.00 1.20 1.40 1.60 1.80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] mode differential mode single-ended signed mode single-ended unsigned mode dnl [lsb] 0.45 0.50 0.55 0.60 0.65 0.70 0.75 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 vref [v]
113 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-41. adc gain error vs. v cc . t = 25 ? c, v ref = 1.0v, adc sample rate = 300ksps . figure 37-42. adc gain error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sample rate = 300ksps gain error [mv] -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] mode differential mode single-ended signed mode single-ended unsigned mode gain error [mv] -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 vref [v] mode differential mode single-ended signed mode single-ended unsigned mode
114 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-43. adc gain error vs. temperature. v cc = 3.6v, v ref = 1.0v, adc sample rate = 300ksps figure 37-44. adc offset error vs. v cc . t = 25 ? c, v ref = 1.0v, adc sample rate = 300ksps gain error [mv] -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 -40 -20 0 20 40 60 80 100 temperature [c] mode differential mode single-ended signed mode single-ended unsigned mode offset [mv] 0.0 5.0 10.0 15.0 20.0 25.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] mode differential mode single-ended signed mode single-ended unsigned mode
115 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-45. adc offset error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sample rate = 300ksps figure 37-46.adc gain error vs. temperature. vcc = 3.6v, vref = external 1.0v, sample rate = 300ksps offset [mv] 5.0 10.0 15.0 20.0 25.0 30.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 vref [v] mode differential mode single-ended signed mode single-ended unsigned mode gain error [mv] -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 -40 -20 0 20 40 60 80 100 temperature [c] mode differential mode single-ended signed mode single-ended unsigned mode
116 xmega e5 [datasheet] 8153f?avr?08/2013 37.4 dac characteristics figure 37-47.dac inl error vs. external v ref . t = 25 ? c, v cc = 3.6v figure 37-48.dnl error vs. v ref . t = 25 ? c, v cc = 3.6v inl [lsb] 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 vref [v] dnl [lsb] 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 vref [v] mode differential mode single-ended signed mode single-ended unsigned mode
117 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-49.dnl error vs. v cc . t = 25 ? c, v ref = 1.0v 37.5 ac characteristics figure 37-50.analog comp arator hysteresis vs. v cc . small hysteresis dnl [lsb] 0.30 0.40 0.50 0.60 0.70 0.80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] mode differential mode single-ended signed mode single-ended unsigned mode vcc [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vhyst [mv] 4 6 8 10 12 14 16 temperature (c) -40 25 85
118 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-51.analog comp arator hysteresis vs. v cc . large hysteresis figure 37-52.analog comparat or propagation delay vs. v cc . figure 37-53.analog comparator propagation delay vs. temperature. vcc [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vhyst [mv] 14 16 18 20 22 24 26 28 30 32 34 temperature (c) -40 25 85 vcc [v] 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 tpd [ns] 10 12 14 16 18 20 22 24 26 temperature (c) -40 25 85 temperature [c] -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 tpd [ns] 10 12 14 16 18 20 22 24 26 vcc (v) 1.6 2 2.7 3 3.3 3.6
119 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-54.analog comparat or current consumption vs. v cc . figure 37-55.analog comparator voltage scaler vs. scalefac. t = 25 ? c, v cc = 3.0v module current consumption [ua] 150 160 170 180 190 200 210 220 230 240 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] tem perature -40 25 85 105 25c -0.150 -0.125 -0.100 -0.075 -0.050 -0.025 0 0.025 0.050 0 10203040506070 scalefac inl [lsb]
120 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-56.analog comparator offs et voltage vs. common mode voltage . figure 37-57.analog comparat or source vs. calibration value . v cc = 3.0v figure 37-58.analog comparat or source vs. calibration value . t = 25 ? c vcm [v] 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 voffset [mv] 0 5 10 15 20 25 30 35 temperature (c) -40 25 85 calib [3..0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i [ua] 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 temperature (c) -40 25 85 calib [3..0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i [ua] 2.0 3.0 4.0 5.0 6.0 7.0 8.0 vcc [v] 1.8 2.2 3 3.6
121 xmega e5 [datasheet] 8153f?avr?08/2013 37.6 internal 1.0v reference characteristics figure 37-59.adc/dac internal 1. 0v reference vs. temperature. 37.7 bod characteristics figure 37-60.bod thresh olds vs. temperature. bod level = 1.6v bandgap voltage [v] 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 temperature [c] vcc 1.6 1.8 2.2 2.7 3 3.3 3.6 vbot [v] 1.61 1.62 1.63 1.64 1.65 1.66 1.67 1.68 1.69 1.70 -30 -15 0 15 30 45 60 75 90 105 temperature [c] test info fall rise
122 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-61.bod thresh olds vs. temperature. bod level = 3.0v 37.8 external reset characteristics figure 37-62.minimum reset pin pulse width vs. v cc . vbot [v] 2.95 3.00 3.05 3.10 -30 -15 0 15 30 45 60 75 90 105 temperature [c] test info fall rise t_rst_ [ns] 80 90 100 110 120 130 140 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] t [c] -40 25 85 105
123 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-63.reset pin pull-up resi stor current vs. reset pin voltage. v cc = 1.8v figure 37-64.reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.0v ireset [ua] -80 -70 -60 -50 -40 -30 -20 -10 0 10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 vreset [v] tem perature -40 25 85 105 ireset [ua] -125 -100 -75 -50 -25 0 25 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 vreset [v] tem perature -40 25 85 105
124 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-65.reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.3v figure 37-66.reset pin inpu t threshold voltage vs. v cc. v ih - reset pin read as ?1? ireset [ua] -150 -125 -100 -75 -50 -25 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 vreset [v] tem perature -40 25 85 105 , v_threshold_ [v] 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] t [c] -40 25 85 105
125 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-67.reset pin inpu t threshold voltage vs. v cc. v il - reset pin read as ?0? 37.9 power-on reset characteristics figure 37-68.power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in continuous mode v_threshold_ [v] 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] t [c] -40 25 85 105 icc [ua] 0 100 200 300 400 500 600 700 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 v_cc_ [v] t [c] -40 25 85 105
126 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-69.power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in sampled mode icc [ua] 0 65 130 195 260 325 390 455 520 585 650 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 v_cc_ [v] t [c] -40 25 85 105
127 xmega e5 [datasheet] 8153f?avr?08/2013 37.10 oscillator characteristics 37.10.1 ultra low-power internal oscillator figure 37-70. ultra low-power internal oscillator frequency vs. temperature. 37.10.2 32.768khz in ternal oscillator figure 37-71. 32.768khz internal o scillator frequency vs. temperature. frequency [khz] 28 29 30 31 32 33 34 35 36 37 -45 -30 -15 0 15 30 45 60 75 90 105 temperature [c] v_cc_ 1.6 1.8 2.2 2.7 3 3.6 frequency [khz] 32.60 32.70 32.80 32.90 33.00 -45 -30 -15 0 15 30 45 60 75 90 105 temperature [c] v_cc_ 1.6 1.8 2.2 2.7 3 3.6
128 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-72. 32.768khz internal oscill ator frequency vs. calibration value. v cc = 3.0v figure 37-73. 32.768khz internal o scillator calibration step size. v cc = 3.0v, t = 25c to 105c frequency [khz] 20.00 25.00 30.00 35.00 40.00 45.00 50.00 0 24 48 72 96 120 144 168 192 216 240 264 cal tem perature -40 25 85 105 frequency step size [%] -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 0 32 64 96 128 160 192 224 256 cal tem perature -40 25 85 105
129 xmega e5 [datasheet] 8153f?avr?08/2013 37.10.3 8mhz internal oscillator figure 37-74. 8mhz internal oscillator frequency vs. temperature. normal mode figure 37-75. 8mhz internal oscillator frequency vs. temperature. low power mode frequency [mhz] 7.960 7.980 8.000 8.020 8.040 8.060 8.080 8.100 8.120 8.140 8.160 -45 -30 -15 0 15 30 45 60 75 90 105 temperature [c] v_cc_[v] 1.6 1.8 2.2 2.7 3 3.6 frequency [mhz] 7.980 8.000 8.020 8.040 8.060 8.080 8.100 8.120 8.140 8.160 -45 -30 -15 0 15 30 45 60 75 90 105 temperature [c] v_cc_ 1.6 1.8 2.2 2.7 3 3.6
130 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-76. 8mhz internal oscill ator cal calibration step size. v cc = 3.0v figure 37-77. 8mhz internal oscillator frequency vs. calibration. v cc = 3.0v, normal mode __ frequency step size [%] 0.00 0.25 0.50 0.75 1.00 1.25 1.50 0 32 64 96 128 160 192 224 256 cal tem perature -40 25 85 105 frequency [mhz] 2.000 4.000 6.000 8.000 10.000 12.000 14.000 16.000 0 32 64 96 128 160 192 224 256 cal tem perature -40 25 85 105
131 xmega e5 [datasheet] 8153f?avr?08/2013 37.10.4 32mhz internal oscillator figure 37-78. 32mhz internal oscillator frequency vs. temperature. dfll disabled figure 37-79. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator frequency [mhz] 30.00 30.50 31.00 31.50 32.00 32.50 33.00 33.50 34.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 temperature [c] v_cc_[v] 1.6 1.8 2.2 2.7 3 3.6 frequency [mhz] 31.88 31.90 31.92 31.94 31.96 31.98 32.00 32.02 32.04 32.06 32.08 32.10 -45 -30 -15 0 15 30 45 60 75 90 105 temperature [c] v_cc_ [v] 1.6 1.8 2.2 2.7 3 3.6
132 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-80. 32mhz internal osci llator cala calibration step size. v cc = 3.0v figure 37-81. 32mhz internal oscillator frequency vs. cala calibration value. v cc = 3.0v frequency step size [%] 0.15 0.16 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0 16 32 48 64 80 96 112 128 cala tem perature -40 25 85 105 frequency [mhz] 38 40 42 44 46 48 50 52 54 0 16 32 48 64 80 96 112 128 cala tem perature -40 25 85 105
133 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-82. 32mhz internal oscillator frequency vs. calb calibration value. v cc = 3.0v 37.11 two-wire interface characteristics figure 37-83. sda fall time vs. temperature. frequency [mhz] 20.00 30.00 40.00 50.00 60.00 70.00 0 8 16 24 32 40 48 56 64 calb tem perature -40 25 85 105 temperature [c] -40 -20 0 20 40 60 80 100 120 fall time [ns] 10 20 30 40 50 60 70 80 mode fast fast + std
134 xmega e5 [datasheet] 8153f?avr?08/2013 figure 37-84. sda fall time vs. v cc . 37.12 pdi characteristics figure 37-85. maximum pdi frequency vs. v cc . vcc [v] 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 fall time [ns] 10 20 30 40 50 60 70 mode fast fast + std maximum frequency [mhz] 6 9 12 15 18 21 24 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 vcc [v] t [c] -40 25 85 105
135 xmega e5 [datasheet] 8153f?avr?08/2013 38. errata ? atxmega32e5 / atxmega16e5 / atxmega8e5 38.1 rev. b ? dac: aref on pd0 is not available for the dac ? adc: offset correction fails in unsigned mode ? eeprom write and flash write operations fails under 2.0v ? twi master or slave remembering data ? twi sm bus level one master or slave remembering data ? temperature sensor not calibrated issue: dac: aref on pd0 is not available for the dac the aref external reference input on pin pd0 is not available for the dac. workaround: no workaround. only aref on pin pa0 can be used as external reference input for the dac. issue: adc: offset correc tion fails in unsigned mode in single ended, unsigned mode, a problem appears in low saturation (zero) when the offset correction is acti- vated. the offset is removed from result and when a negative result appears, the result is not correct. workaround: no workaround, but avoid using this correction method to cancel ? v effect. issue: eeprom write and flash wr ite operations fa ils under 2.0v eeprom write and flash write operations are limited from 2. 0v to 3.6v. other functionalities operates from 1.6v to 3.6v. workaround: none. issue: twi master or slave remembering data if a write is made to data register, prior to address register, the twi design sends the data as soon as the write to address register is made. but the send data will be always 0x00. workaround: none.
136 xmega e5 [datasheet] 8153f?avr?08/2013 issue: twi sm bus level one master or slave remembering data if a write is made to data register, prior to address register, the twi design sends the data as soon as the write to address register is made. but the send data will be always 0x00. workaround: since single interrupt line is shared by both timeout interrupt and other twi interrupt sources, there is a possibility in software that data register will be written after timeout is detected but before timeout interrupt routine is exe- cuted. to avoid this, in software, before writing data register, always ensure that timeout status flag is not set. issue: temperature sensor not calibrated temperature sensor factory calibration is not implemented on devices before date code 1324. workaround: none.
137 xmega e5 [datasheet] 8153f?avr?08/2013 38.2 rev. a ? dac: aref on pd0 is not available for the dac ? edma: channel transfer never stops when double buffering is enabled on sub-sequent channels ? adc: offset correction fails in unsigned mode ? adc: averaging is failing when channel scan is enabled ? adc: averaging in single conversion requires multiple conversion triggers ? adc accumulator sign extends the result in unsigned mode averaging ? adc: free running average mode issue ? adc: event triggered conversion in averaging mode ? ac: flag can not be cleared if the module is not enabled ? usart: receiver not functional when variabl e data length and start frame detector are enabled ? t/c: counter does not start when clksel is written ? eeprom write and flash write operations fails under 2.0v ? twi master or slave remembering data ? temperature sensor not calibrated issue: dac: aref on pd0 is not available for the dac the aref external reference input on pin pd0 is not available for the dac. workaround: no workaround. only aref on pin pa0 can be used as external reference input for the dac. issue: edma: channel transfer never stops when double buffering is enabled on sub-sequent channels when the double buffering is enabled on two channels, the channels which are not set in double buffering mode are never disabled at the end of the transfer. a new transfer can start if the channel is not disabled by software. workaround: ? chmode = 00 enable double buffering on all channels or do not use channels which are not set the double buffering mode. ? chmode = 01 or 10 do not use the channel which is not supporting the double buffering mode. issue: adc: offset correc tion fails in unsigned mode in single ended, unsigned mode, a problem appears in low saturation (zero) when the offset correction is acti- vated. the offset is removed from result and when a negative result appears, the result is not correct. workaround: no workaround, but avoid using this correction method to cancel ? v effect.
138 xmega e5 [datasheet] 8153f?avr?08/2013 issue: adc: averaging is failing when channel scan is enabled for a correct operation, the averaging must complete on the on-going channel before incrementing the input off- set. in the current implementation, the input offset is incremented after the adc sampling is done. workaround: none. issue: adc: averaging in single conversion requires multiple conversion triggers for a normal operation, an unique start of conversion tri gger starts a complete average operation. then, for n- samples average operation, we should have: ? one start of conversion ? n conversions + average ? optional interrupt when the nth conversion/last average is completed on silicon we need: ? n start of conversion the two additional steps are well done. workaround: ? set averaging configuration ? n starts of conversion by polling the reset of start bit ? wait for interrupt flag (end of averaging) issue: adc accumulator sign extends the result in unsigned mode averaging in unsigned mode averaging, when the msb is going hi gh(1), measurements are considered as negative when right shift is used. this sets the unused most significant bits once the shift is done. workaround: mask to zero the unused most significant bits once shift is done. issue: adc: free running average mode issue in free running mode the adc stops the ongoing averaging as soon as free running bit is disabled. this creates the need to flush the adc before starting the next conversion since one or two conversions might have taken place in the internal accumulator. workaround: disable and re-enable the adc before the start of next conversion in free running average mode. issue: adc: event triggered conversion in averaging mode if the adc is configured as event triggered in averaging mode, then a single event does not complete the entire averaging as it should be. workaround: in the current revision, n events are needed for completing averaging on n samples.
139 xmega e5 [datasheet] 8153f?avr?08/2013 issue: ac: flag can not be cleared if the module is not enabled it is not possible to clear the ac interrupt fl ags without enabling either of the analog comparators. workaround: clear the interrupt flags before disabling the module. issue: usart: receiver not functional when variable data length and start frame detector are enabled when using usart in variable frame length with xcl pe c01 configuration and start frame detection activated, the usart receiver is not functional. workaround: use xcl btc0pce2 configuration instead of pec01. issue: t/c: counter does not start when clksel is written when stop bit is cleared (ctrlgclr.stop) before the ti mer/counter is enabled (ctr la.clksel != off), the t/c doesn't start operation. workaround: do not write ctrlgclr.stop bit before writing ctrla.clksel bits. issue: eeprom write and flash wr ite operations fa ils under 2.0v eeprom write and flash write operations are limited from 2. 0v to 3.6v. other functionalities operates from 1.6v to 3.6v. workaround: none. issue: twi master or slave remembering data if a write is made to data register, prior to address register, the twi design sends the data as soon as the write to address register is made. but the send data will be always 0x00. workaround: none. issue: temperature sensor not calibrated temperature sensor factory calibration is not implemented. workaround: none.
140 xmega e5 [datasheet] 8153f?avr?08/2013 39. revision history please note that referring page numbers in this section are referred to this document. the referring revision in this document section are referring to the document revision. 39.1 8135f ? 08/2013 39.2 8135e ? 06/2013 39.3 8135d ? 06/2013 39.4 8135c ? 05/2013 39.5 8153b ? 04/2013 39.6 8153a ? 04/2013 1. twi characteristics: unit s of data setup time (t su;dat ) changed from s to ns in table 36-30 on page 91 . 1. errata ?rev. b? : updated date code from 1318 to 1324 in ?temperature sensor not calibrated? on page 136 . 1. analog comparator characteristics: updated minimu m and maximum values of input voltage range, table 36-14 on page 81 . 1. electrical characteristics, table 36-3 on page 73 : updated typical value from 7ma to 6ma for active current consumption, 32mhz, v cc =3.0v. 2. errata ?rev. a? and ?rev. b? : added dac errata: aref on port c0. 1. ?rev. b? on page 135 : removed the ?edma: channel transfer never stops when double buffering is enabled on sub-sequent channels? errata. 1. initial revision.
i xmega e5 [datasheet] 8153f?avr?08/2013 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. pinout and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5. resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1 recommended reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6. capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7. cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.3 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.4 alu - arithmetic logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.5 program flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.6 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.7 stack and stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.8 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8. memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.3 flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.4 fuses and lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.5 data memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.6 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.7 i/o memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.8 data memory and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.9 memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.10 device id and revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.11 i/o memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.12 flash and eeprom page size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9. edma ? enhanced dma controller . . . . . . . . . . . . . . . . . . . . . . . . 15 9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10. event system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11. system clock and clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.3 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ii xmega e5 [datasheet] 8153f?avr?08/2013 12. power management and sleep modes . . . . . . . . . . . . . . . . . . . . . . 22 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12.3 sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13. system control and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.3 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.4 reset sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14. wdt ? watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15. interrupts and programmable multilevel interrupt controller . . . . . . 27 15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 15.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 15.3 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16. i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16.3 output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16.4 input sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 16.5 alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17. timer counter type 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 17.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 18. wex ? waveform extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 18.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 19. hi-res ? high resolution extension . . . . . . . . . . . . . . . . . . . . . . . . 37 19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 19.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 20. fault extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 21. rtc ? 16-bit real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 21.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 22. twi ? two wire interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 22.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 23. spi ? serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
iii xmega e5 [datasheet] 8153f?avr?08/2013 23.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 24. usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 25. ircom ? ir communication module . . . . . . . . . . . . . . . . . . . . . . . 46 25.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 25.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 26. xcl ? xmega custom logic module . . . . . . . . . . . . . . . . . . . . . . . 47 26.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 26.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 27. crc ? cyclic redundancy check generator . . . . . . . . . . . . . . . . . 49 27.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 27.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 28. adc ? 12-bit analog to digital converter . . . . . . . . . . . . . . . . . . . . 50 28.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 28.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 29. dac ? digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . 52 29.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 29.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 30. ac ? analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 30.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 30.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 31. programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 31.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 31.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 32. pinout and pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 32.1 alternate pin function descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 32.2 alternate pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 33. peripheral module address map . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 34. instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 35. packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 35.1 32a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 35.2 32z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 35.3 32ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 36. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 36.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 36.2 general operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 36.3 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 36.4 wake-up time from sleep modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 36.5 i/o pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 36.6 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
iv xmega e5 [datasheet] 8153f?avr?08/2013 36.7 dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 36.8 analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 36.9 bandgap and internal 1.0v reference characteristics . . . . . . . . . . . . . . . . . . 81 36.10 external reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 36.11 power-on reset characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 36.12 flash and eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 36.13 clock and oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 36.14 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 36.15 two-wire interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 37. typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 37.1 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 37.2 i/o pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 37.3 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 37.4 dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 37.5 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 37.6 internal 1.0v reference characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 37.7 bod characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 37.8 external reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 37.9 power-on reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 37.10 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 37.11 two-wire interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 37.12 pdi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 38. errata ? atxmega32e5 / atxmega16e5 / atxmega8e5 . . . . . . . 135 38.1 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 38.2 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 39. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 39.1 8135f ? 08/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 39.2 8135e ? 06/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 39.3 8135d ? 06/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 39.4 8135c ? 05/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 39.5 8153b ? 04/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 39.6 8153a ? 04/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 8153f?avr?08/2013 atmel?, atmel logo and combinations thereof, enabling unlimited possibilities?, avr?, xmega? and others are registered trademar ks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in co nnection with atmel products. no lic ense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life.

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